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![Vineet Gupta](/assets/img/avatar_default.png)
The primary interrupt handler arch_do_IRQ() was passing hwirq as linux virq to core code. This was fragile and worked so far as we only had legacy/linear domains. This came out of a rant by Marc Zyngier. http://lists.infradead.org/pipermail/linux-snps-arc/2015-December/000298.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Noam Camus <noamc@ezchip.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/*
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* Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <asm/mach_desc.h>
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#include <asm/smp.h>
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/*
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* Late Interrupt system init called from start_kernel for Boot CPU only
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*
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* Since slab must already be initialized, platforms can start doing any
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* needed request_irq( )s
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*/
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void __init init_IRQ(void)
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{
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/*
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* process the entire interrupt tree in one go
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* Any external intc will be setup provided DT chains them
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* properly
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*/
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irqchip_init();
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#ifdef CONFIG_SMP
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/* a SMP H/w block could do IPI IRQ request here */
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if (plat_smp_ops.init_per_cpu)
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plat_smp_ops.init_per_cpu(smp_processor_id());
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if (machine_desc->init_per_cpu)
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machine_desc->init_per_cpu(smp_processor_id());
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#endif
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}
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/*
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* "C" Entry point for any ARC ISR, called from low level vector handler
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* @irq is the vector number read from ICAUSE reg of on-chip intc
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*/
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void arch_do_IRQ(unsigned int hwirq, struct pt_regs *regs)
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{
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handle_domain_irq(NULL, hwirq, regs);
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}
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