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![Christophe Leroy](/assets/img/avatar_default.png)
CONFIG_PIN_TLB maps IMMR area and the first 24 Mbytes of memory. In some circunstances it might be more interesting to not map IMMR but map 32 Mbytes of memory instead. Therefore we add config option CONFIG_PIN_TLB_IMMR to select if IMMR shall be pinned or not, hence whether we pin 24 or 32 Mbytes of RAM Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
190 lines
4.7 KiB
C
190 lines
4.7 KiB
C
/*
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* This file contains the routines for initializing the MMU
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* on the 8xx series of chips.
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* -- christophe
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*
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* Derived from arch/powerpc/mm/40x_mmu.c:
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/memblock.h>
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#include <asm/fixmap.h>
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#include <asm/code-patching.h>
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#include "mmu_decl.h"
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#define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT)
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extern int __map_without_ltlbs;
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/*
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* Return PA for this VA if it is in IMMR area, or 0
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*/
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phys_addr_t v_block_mapped(unsigned long va)
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{
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unsigned long p = PHYS_IMMR_BASE;
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if (__map_without_ltlbs)
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return 0;
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if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE)
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return p + va - VIRT_IMMR_BASE;
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return 0;
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}
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/*
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* Return VA for a given PA or 0 if not mapped
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*/
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unsigned long p_block_mapped(phys_addr_t pa)
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{
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unsigned long p = PHYS_IMMR_BASE;
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if (__map_without_ltlbs)
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return 0;
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if (pa >= p && pa < p + IMMR_SIZE)
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return VIRT_IMMR_BASE + pa - p;
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return 0;
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}
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#define LARGE_PAGE_SIZE_8M (1<<23)
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/*
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* MMU_init_hw does the chip-specific initialization of the MMU hardware.
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*/
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void __init MMU_init_hw(void)
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{
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/* PIN up to the 3 first 8Mb after IMMR in DTLB table */
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#ifdef CONFIG_PIN_TLB
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unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000;
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unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY;
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#ifdef CONFIG_PIN_TLB_IMMR
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int i = 29;
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#else
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int i = 28;
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#endif
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unsigned long addr = 0;
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unsigned long mem = total_lowmem;
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for (; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) {
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mtspr(SPRN_MD_CTR, ctr | (i << 8));
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mtspr(SPRN_MD_EPN, (unsigned long)__va(addr) | MD_EVALID);
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mtspr(SPRN_MD_TWC, MD_PS8MEG | MD_SVALID);
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mtspr(SPRN_MD_RPN, addr | flags | _PAGE_PRESENT);
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addr += LARGE_PAGE_SIZE_8M;
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mem -= LARGE_PAGE_SIZE_8M;
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}
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#endif
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}
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static void mmu_mapin_immr(void)
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{
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unsigned long p = PHYS_IMMR_BASE;
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unsigned long v = VIRT_IMMR_BASE;
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unsigned long f = pgprot_val(PAGE_KERNEL_NCG);
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int offset;
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for (offset = 0; offset < IMMR_SIZE; offset += PAGE_SIZE)
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map_page(v + offset, p + offset, f);
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}
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/* Address of instructions to patch */
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#ifndef CONFIG_PIN_TLB_IMMR
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extern unsigned int DTLBMiss_jmp;
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#endif
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extern unsigned int DTLBMiss_cmp, FixupDAR_cmp;
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void mmu_patch_cmp_limit(unsigned int *addr, unsigned long mapped)
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{
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unsigned int instr = *addr;
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instr &= 0xffff0000;
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instr |= (unsigned long)__va(mapped) >> 16;
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patch_instruction(addr, instr);
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}
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unsigned long __init mmu_mapin_ram(unsigned long top)
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{
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unsigned long mapped;
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if (__map_without_ltlbs) {
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mapped = 0;
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mmu_mapin_immr();
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#ifndef CONFIG_PIN_TLB_IMMR
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patch_instruction(&DTLBMiss_jmp, PPC_INST_NOP);
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#endif
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} else {
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mapped = top & ~(LARGE_PAGE_SIZE_8M - 1);
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}
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mmu_patch_cmp_limit(&DTLBMiss_cmp, mapped);
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mmu_patch_cmp_limit(&FixupDAR_cmp, mapped);
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/* If the size of RAM is not an exact power of two, we may not
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* have covered RAM in its entirety with 8 MiB
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* pages. Consequently, restrict the top end of RAM currently
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* allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
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* coverage with normal-sized pages (or other reasons) do not
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* attempt to allocate outside the allowed range.
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*/
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if (mapped)
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memblock_set_current_limit(mapped);
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return mapped;
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}
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void setup_initial_memory_limit(phys_addr_t first_memblock_base,
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phys_addr_t first_memblock_size)
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{
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/* We don't currently support the first MEMBLOCK not mapping 0
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* physical on those processors
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*/
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BUG_ON(first_memblock_base != 0);
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/* 8xx can only access 24MB at the moment */
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memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
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}
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/*
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* Set up to use a given MMU context.
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* id is context number, pgd is PGD pointer.
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*
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* We place the physical address of the new task page directory loaded
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* into the MMU base register, and set the ASID compare register with
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* the new "context."
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*/
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void set_context(unsigned long id, pgd_t *pgd)
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{
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s16 offset = (s16)(__pa(swapper_pg_dir));
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#ifdef CONFIG_BDI_SWITCH
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pgd_t **ptr = *(pgd_t ***)(KERNELBASE + 0xf0);
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/* Context switch the PTE pointer for the Abatron BDI2000.
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* The PGDIR is passed as second argument.
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*/
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*(ptr + 1) = pgd;
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#endif
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/* Register M_TW will contain base address of level 1 table minus the
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* lower part of the kernel PGDIR base address, so that all accesses to
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* level 1 table are done relative to lower part of kernel PGDIR base
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* address.
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*/
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mtspr(SPRN_M_TW, __pa(pgd) - offset);
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/* Update context */
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mtspr(SPRN_M_CASID, id);
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/* sync */
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mb();
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}
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void flush_instruction_cache(void)
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{
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isync();
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mtspr(SPRN_IC_CST, IDC_INVALL);
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isync();
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}
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