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4badd43ae4
Once the linear memory space has been mapped with 8Mb pages, as seen in the related commit, we get 11 millions DTLB missed during the reference 600s period. 77% of the misses are on user addresses and 23% are on kernel addresses (1 fourth for linear address space and 3 fourth for virtual address space) Traditionaly, each driver manages one computer board which has its own components with its own memory maps. But on embedded chips like the MPC8xx, the SOC has all registers located in the same IO area. When looking at ioremaps done during startup, we see that many drivers are re-mapping small parts of the IMMR for their own use and all those small pieces gets their own 4k page, amplifying the number of TLB misses: in our system we get 0xff000000 mapped 31 times and 0xff003000 mapped 9 times. Even if each part of IMMR was mapped only once with 4k pages, it would still be several small mappings towards linear area. This patch maps the IMMR with a single 512k page. With this patch applied, the number of DTLB misses during the 10 min period is reduced to 11.8 millions for a duration of 5.8s, which represents 2% of the non-idle time hence yet another 10% reduction. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
166 lines
4.7 KiB
C
166 lines
4.7 KiB
C
/*
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* Declarations of procedures and variables shared between files
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* in arch/ppc/mm/.
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/mm.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_PPC_MMU_NOHASH
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/*
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* On 40x and 8xx, we directly inline tlbia and tlbivax
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*/
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#if defined(CONFIG_40x) || defined(CONFIG_8xx)
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static inline void _tlbil_all(void)
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{
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asm volatile ("sync; tlbia; isync" : : : "memory");
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}
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static inline void _tlbil_pid(unsigned int pid)
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{
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asm volatile ("sync; tlbia; isync" : : : "memory");
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}
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#define _tlbil_pid_noind(pid) _tlbil_pid(pid)
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#else /* CONFIG_40x || CONFIG_8xx */
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extern void _tlbil_all(void);
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extern void _tlbil_pid(unsigned int pid);
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#ifdef CONFIG_PPC_BOOK3E
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extern void _tlbil_pid_noind(unsigned int pid);
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#else
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#define _tlbil_pid_noind(pid) _tlbil_pid(pid)
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#endif
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#endif /* !(CONFIG_40x || CONFIG_8xx) */
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/*
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* On 8xx, we directly inline tlbie, on others, it's extern
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*/
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#ifdef CONFIG_8xx
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static inline void _tlbil_va(unsigned long address, unsigned int pid,
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unsigned int tsize, unsigned int ind)
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{
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asm volatile ("tlbie %0; sync" : : "r" (address) : "memory");
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}
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#elif defined(CONFIG_PPC_BOOK3E)
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extern void _tlbil_va(unsigned long address, unsigned int pid,
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unsigned int tsize, unsigned int ind);
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#else
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extern void __tlbil_va(unsigned long address, unsigned int pid);
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static inline void _tlbil_va(unsigned long address, unsigned int pid,
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unsigned int tsize, unsigned int ind)
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{
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__tlbil_va(address, pid);
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}
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#endif /* CONFIG_8xx */
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#if defined(CONFIG_PPC_BOOK3E) || defined(CONFIG_PPC_47x)
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extern void _tlbivax_bcast(unsigned long address, unsigned int pid,
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unsigned int tsize, unsigned int ind);
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#else
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static inline void _tlbivax_bcast(unsigned long address, unsigned int pid,
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unsigned int tsize, unsigned int ind)
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{
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BUG();
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}
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#endif
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#else /* CONFIG_PPC_MMU_NOHASH */
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extern void hash_preload(struct mm_struct *mm, unsigned long ea,
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unsigned long access, unsigned long trap);
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extern void _tlbie(unsigned long address);
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extern void _tlbia(void);
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#endif /* CONFIG_PPC_MMU_NOHASH */
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#ifdef CONFIG_PPC32
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extern void mapin_ram(void);
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extern int map_page(unsigned long va, phys_addr_t pa, int flags);
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extern void setbat(int index, unsigned long virt, phys_addr_t phys,
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unsigned int size, pgprot_t prot);
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extern int __map_without_bats;
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extern int __allow_ioremap_reserved;
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extern unsigned int rtas_data, rtas_size;
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struct hash_pte;
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extern struct hash_pte *Hash, *Hash_end;
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extern unsigned long Hash_size, Hash_mask;
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#endif /* CONFIG_PPC32 */
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extern unsigned long ioremap_bot;
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extern unsigned long __max_low_memory;
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extern phys_addr_t __initial_memory_limit_addr;
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extern phys_addr_t total_memory;
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extern phys_addr_t total_lowmem;
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extern phys_addr_t memstart_addr;
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extern phys_addr_t lowmem_end_addr;
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#ifdef CONFIG_WII
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extern unsigned long wii_hole_start;
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extern unsigned long wii_hole_size;
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extern unsigned long wii_mmu_mapin_mem2(unsigned long top);
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extern void wii_memory_fixups(void);
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#endif
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/* ...and now those things that may be slightly different between processor
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* architectures. -- Dan
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*/
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#ifdef CONFIG_PPC32
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extern void MMU_init_hw(void);
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extern unsigned long mmu_mapin_ram(unsigned long top);
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#endif
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#ifdef CONFIG_PPC_FSL_BOOK3E
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extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx,
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bool dryrun);
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extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
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phys_addr_t phys);
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#ifdef CONFIG_PPC32
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extern void adjust_total_lowmem(void);
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extern int switch_to_as1(void);
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extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
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#endif
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extern void loadcam_entry(unsigned int index);
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extern void loadcam_multi(int first_idx, int num, int tmp_idx);
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struct tlbcam {
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u32 MAS0;
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u32 MAS1;
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unsigned long MAS2;
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u32 MAS3;
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u32 MAS7;
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};
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#endif
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#if defined(CONFIG_6xx) || defined(CONFIG_FSL_BOOKE) || defined(CONFIG_PPC_8xx)
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/* 6xx have BATS */
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/* FSL_BOOKE have TLBCAM */
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/* 8xx have LTLB */
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phys_addr_t v_block_mapped(unsigned long va);
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unsigned long p_block_mapped(phys_addr_t pa);
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#else
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static inline phys_addr_t v_block_mapped(unsigned long va) { return 0; }
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static inline unsigned long p_block_mapped(phys_addr_t pa) { return 0; }
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#endif
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