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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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1e688dd2a3
Using asm goto in __WARN_FLAGS() and WARN_ON() allows more
flexibility to GCC.
For that add an entry to the exception table so that
program_check_exception() knowns where to resume execution
after a WARNING.
Here are two exemples. The first one is done on PPC32 (which
benefits from the previous patch), the second is on PPC64.
unsigned long test(struct pt_regs *regs)
{
int ret;
WARN_ON(regs->msr & MSR_PR);
return regs->gpr[3];
}
unsigned long test9w(unsigned long a, unsigned long b)
{
if (WARN_ON(!b))
return 0;
return a / b;
}
Before the patch:
000003a8 <test>:
3a8: 81 23 00 84 lwz r9,132(r3)
3ac: 71 29 40 00 andi. r9,r9,16384
3b0: 40 82 00 0c bne 3bc <test+0x14>
3b4: 80 63 00 0c lwz r3,12(r3)
3b8: 4e 80 00 20 blr
3bc: 0f e0 00 00 twui r0,0
3c0: 80 63 00 0c lwz r3,12(r3)
3c4: 4e 80 00 20 blr
0000000000000bf0 <.test9w>:
bf0: 7c 89 00 74 cntlzd r9,r4
bf4: 79 29 d1 82 rldicl r9,r9,58,6
bf8: 0b 09 00 00 tdnei r9,0
bfc: 2c 24 00 00 cmpdi r4,0
c00: 41 82 00 0c beq c0c <.test9w+0x1c>
c04: 7c 63 23 92 divdu r3,r3,r4
c08: 4e 80 00 20 blr
c0c: 38 60 00 00 li r3,0
c10: 4e 80 00 20 blr
After the patch:
000003a8 <test>:
3a8: 81 23 00 84 lwz r9,132(r3)
3ac: 71 29 40 00 andi. r9,r9,16384
3b0: 40 82 00 0c bne 3bc <test+0x14>
3b4: 80 63 00 0c lwz r3,12(r3)
3b8: 4e 80 00 20 blr
3bc: 0f e0 00 00 twui r0,0
0000000000000c50 <.test9w>:
c50: 7c 89 00 74 cntlzd r9,r4
c54: 79 29 d1 82 rldicl r9,r9,58,6
c58: 0b 09 00 00 tdnei r9,0
c5c: 7c 63 23 92 divdu r3,r3,r4
c60: 4e 80 00 20 blr
c70: 38 60 00 00 li r3,0
c74: 4e 80 00 20 blr
In the first exemple, we see GCC doesn't need to duplicate what
happens after the trap.
In the second exemple, we see that GCC doesn't need to emit a test
and a branch in the likely path in addition to the trap.
We've got some WARN_ON() in .softirqentry.text section so it needs
to be added in the OTHER_TEXT_SECTIONS in modpost.c
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/389962b1b702e3c78d169e59bcfac56282889173.1618331882.git.christophe.leroy@csgroup.eu
479 lines
12 KiB
ArmAsm
479 lines
12 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This file contains the system call entry code, context switch
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* code, and exception/interrupt return code for PowerPC.
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*/
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <asm/cache.h>
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#include <asm/unistd.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/thread_info.h>
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#include <asm/code-patching-asm.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/firmware.h>
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#include <asm/bug.h>
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#include <asm/ptrace.h>
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#include <asm/irqflags.h>
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#include <asm/hw_irq.h>
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#include <asm/context_tracking.h>
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#include <asm/ppc-opcode.h>
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#include <asm/barrier.h>
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#include <asm/export.h>
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#include <asm/asm-compat.h>
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/exception-64s.h>
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#else
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#include <asm/exception-64e.h>
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#endif
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#include <asm/feature-fixups.h>
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#include <asm/kup.h>
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/*
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* System calls.
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*/
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.section ".text"
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#ifdef CONFIG_PPC_BOOK3S_64
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#define FLUSH_COUNT_CACHE \
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1: nop; \
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patch_site 1b, patch__call_flush_branch_caches1; \
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1: nop; \
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patch_site 1b, patch__call_flush_branch_caches2; \
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1: nop; \
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patch_site 1b, patch__call_flush_branch_caches3
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.macro nops number
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.rept \number
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nop
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.endr
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.endm
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.balign 32
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.global flush_branch_caches
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flush_branch_caches:
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/* Save LR into r9 */
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mflr r9
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// Flush the link stack
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.rept 64
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bl .+4
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.endr
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b 1f
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nops 6
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.balign 32
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/* Restore LR */
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1: mtlr r9
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// If we're just flushing the link stack, return here
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3: nop
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patch_site 3b patch__flush_link_stack_return
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li r9,0x7fff
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mtctr r9
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PPC_BCCTR_FLUSH
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2: nop
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patch_site 2b patch__flush_count_cache_return
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nops 3
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.rept 278
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.balign 32
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PPC_BCCTR_FLUSH
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nops 7
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.endr
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blr
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#else
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#define FLUSH_COUNT_CACHE
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#endif /* CONFIG_PPC_BOOK3S_64 */
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/*
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* This routine switches between two different tasks. The process
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* state of one is saved on its kernel stack. Then the state
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* of the other is restored from its kernel stack. The memory
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* management hardware is updated to the second process's state.
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* Finally, we can return to the second process, via interrupt_return.
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* On entry, r3 points to the THREAD for the current task, r4
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* points to the THREAD for the new task.
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*
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* Note: there are two ways to get to the "going out" portion
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* of this code; either by coming in via the entry (_switch)
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* or via "fork" which must set up an environment equivalent
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* to the "_switch" path. If you change this you'll have to change
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* the fork code also.
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*
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* The code which creates the new task context is in 'copy_thread'
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* in arch/powerpc/kernel/process.c
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*/
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.align 7
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_GLOBAL(_switch)
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mflr r0
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std r0,16(r1)
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stdu r1,-SWITCH_FRAME_SIZE(r1)
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/* r3-r13 are caller saved -- Cort */
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SAVE_NVGPRS(r1)
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std r0,_NIP(r1) /* Return to switch caller */
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mfcr r23
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std r23,_CCR(r1)
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std r1,KSP(r3) /* Set old stack pointer */
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kuap_check_amr r9, r10
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FLUSH_COUNT_CACHE /* Clobbers r9, ctr */
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/*
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* On SMP kernels, care must be taken because a task may be
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* scheduled off CPUx and on to CPUy. Memory ordering must be
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* considered.
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*
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* Cacheable stores on CPUx will be visible when the task is
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* scheduled on CPUy by virtue of the core scheduler barriers
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* (see "Notes on Program-Order guarantees on SMP systems." in
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* kernel/sched/core.c).
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*
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* Uncacheable stores in the case of involuntary preemption must
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* be taken care of. The smp_mb__after_spinlock() in __schedule()
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* is implemented as hwsync on powerpc, which orders MMIO too. So
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* long as there is an hwsync in the context switch path, it will
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* be executed on the source CPU after the task has performed
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* all MMIO ops on that CPU, and on the destination CPU before the
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* task performs any MMIO ops there.
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*/
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/*
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* The kernel context switch path must contain a spin_lock,
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* which contains larx/stcx, which will clear any reservation
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* of the task being switched.
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*/
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#ifdef CONFIG_PPC_BOOK3S
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/* Cancel all explict user streams as they will have no use after context
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* switch and will stop the HW from creating streams itself
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*/
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DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r6)
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#endif
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addi r6,r4,-THREAD /* Convert THREAD to 'current' */
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std r6,PACACURRENT(r13) /* Set new 'current' */
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#if defined(CONFIG_STACKPROTECTOR)
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ld r6, TASK_CANARY(r6)
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std r6, PACA_CANARY(r13)
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#endif
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ld r8,KSP(r4) /* new stack pointer */
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#ifdef CONFIG_PPC_BOOK3S_64
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BEGIN_MMU_FTR_SECTION
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b 2f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
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BEGIN_FTR_SECTION
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clrrdi r6,r8,28 /* get its ESID */
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clrrdi r9,r1,28 /* get current sp ESID */
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FTR_SECTION_ELSE
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clrrdi r6,r8,40 /* get its 1T ESID */
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clrrdi r9,r1,40 /* get current sp 1T ESID */
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
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clrldi. r0,r6,2 /* is new ESID c00000000? */
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cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
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cror eq,4*cr1+eq,eq
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beq 2f /* if yes, don't slbie it */
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/* Bolt in the new stack SLB entry */
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ld r7,KSP_VSID(r4) /* Get new stack's VSID */
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oris r0,r6,(SLB_ESID_V)@h
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ori r0,r0,(SLB_NUM_BOLTED-1)@l
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BEGIN_FTR_SECTION
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li r9,MMU_SEGSIZE_1T /* insert B field */
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oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
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rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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/* Update the last bolted SLB. No write barriers are needed
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* here, provided we only update the current CPU's SLB shadow
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* buffer.
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*/
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ld r9,PACA_SLBSHADOWPTR(r13)
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li r12,0
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std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
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li r12,SLBSHADOW_STACKVSID
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STDX_BE r7,r12,r9 /* Save VSID */
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li r12,SLBSHADOW_STACKESID
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STDX_BE r0,r12,r9 /* Save ESID */
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/* No need to check for MMU_FTR_NO_SLBIE_B here, since when
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* we have 1TB segments, the only CPUs known to have the errata
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* only support less than 1TB of system memory and we'll never
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* actually hit this code path.
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*/
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isync
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slbie r6
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BEGIN_FTR_SECTION
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slbie r6 /* Workaround POWER5 < DD2.1 issue */
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END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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slbmte r7,r0
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isync
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2:
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#endif /* CONFIG_PPC_BOOK3S_64 */
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clrrdi r7, r8, THREAD_SHIFT /* base of new stack */
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/* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
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because we don't need to leave the 288-byte ABI gap at the
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top of the kernel stack. */
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addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
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/*
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* PMU interrupts in radix may come in here. They will use r1, not
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* PACAKSAVE, so this stack switch will not cause a problem. They
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* will store to the process stack, which may then be migrated to
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* another CPU. However the rq lock release on this CPU paired with
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* the rq lock acquire on the new CPU before the stack becomes
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* active on the new CPU, will order those stores.
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*/
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mr r1,r8 /* start using new stack pointer */
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std r7,PACAKSAVE(r13)
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ld r6,_CCR(r1)
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mtcrf 0xFF,r6
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/* r3-r13 are destroyed -- Cort */
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REST_NVGPRS(r1)
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/* convert old thread to its task_struct for return value */
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addi r3,r3,-THREAD
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ld r7,_NIP(r1) /* Return to _switch caller in new task */
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mtlr r7
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addi r1,r1,SWITCH_FRAME_SIZE
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blr
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#ifdef CONFIG_PPC_RTAS
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/*
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* On CHRP, the Run-Time Abstraction Services (RTAS) have to be
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* called with the MMU off.
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*
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* In addition, we need to be in 32b mode, at least for now.
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*
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* Note: r3 is an input parameter to rtas, so don't trash it...
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*/
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_GLOBAL(enter_rtas)
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mflr r0
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std r0,16(r1)
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stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space. */
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/* Because RTAS is running in 32b mode, it clobbers the high order half
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* of all registers that it saves. We therefore save those registers
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* RTAS might touch to the stack. (r0, r3-r13 are caller saved)
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*/
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SAVE_GPR(2, r1) /* Save the TOC */
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SAVE_GPR(13, r1) /* Save paca */
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SAVE_NVGPRS(r1) /* Save the non-volatiles */
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mfcr r4
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std r4,_CCR(r1)
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mfctr r5
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std r5,_CTR(r1)
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mfspr r6,SPRN_XER
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std r6,_XER(r1)
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mfdar r7
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std r7,_DAR(r1)
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mfdsisr r8
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std r8,_DSISR(r1)
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/* Temporary workaround to clear CR until RTAS can be modified to
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* ignore all bits.
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*/
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li r0,0
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mtcr r0
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#ifdef CONFIG_BUG
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/* There is no way it is acceptable to get here with interrupts enabled,
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* check it with the asm equivalent of WARN_ON
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*/
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lbz r0,PACAIRQSOFTMASK(r13)
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1: tdeqi r0,IRQS_ENABLED
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EMIT_WARN_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
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#endif
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/* Hard-disable interrupts */
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mfmsr r6
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rldicl r7,r6,48,1
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rotldi r7,r7,16
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mtmsrd r7,1
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/* Unfortunately, the stack pointer and the MSR are also clobbered,
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* so they are saved in the PACA which allows us to restore
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* our original state after RTAS returns.
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*/
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std r1,PACAR1(r13)
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std r6,PACASAVEDMSR(r13)
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/* Setup our real return addr */
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LOAD_REG_ADDR(r4,rtas_return_loc)
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clrldi r4,r4,2 /* convert to realmode address */
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mtlr r4
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li r0,0
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ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
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andc r0,r6,r0
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li r9,1
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rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
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ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
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andc r6,r0,r9
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__enter_rtas:
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sync /* disable interrupts so SRR0/1 */
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mtmsrd r0 /* don't get trashed */
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LOAD_REG_ADDR(r4, rtas)
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ld r5,RTASENTRY(r4) /* get the rtas->entry value */
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ld r4,RTASBASE(r4) /* get the rtas->base value */
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mtspr SPRN_SRR0,r5
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mtspr SPRN_SRR1,r6
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RFI_TO_KERNEL
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b . /* prevent speculative execution */
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rtas_return_loc:
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FIXUP_ENDIAN
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/*
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* Clear RI and set SF before anything.
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*/
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mfmsr r6
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li r0,MSR_RI
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andc r6,r6,r0
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sldi r0,r0,(MSR_SF_LG - MSR_RI_LG)
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or r6,r6,r0
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sync
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mtmsrd r6
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/* relocation is off at this point */
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GET_PACA(r4)
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clrldi r4,r4,2 /* convert to realmode address */
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bcl 20,31,$+4
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0: mflr r3
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ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
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ld r1,PACAR1(r4) /* Restore our SP */
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ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
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mtspr SPRN_SRR0,r3
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mtspr SPRN_SRR1,r4
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RFI_TO_KERNEL
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b . /* prevent speculative execution */
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_ASM_NOKPROBE_SYMBOL(__enter_rtas)
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_ASM_NOKPROBE_SYMBOL(rtas_return_loc)
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.align 3
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1: .8byte rtas_restore_regs
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rtas_restore_regs:
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/* relocation is on at this point */
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REST_GPR(2, r1) /* Restore the TOC */
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REST_GPR(13, r1) /* Restore paca */
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REST_NVGPRS(r1) /* Restore the non-volatiles */
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GET_PACA(r13)
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ld r4,_CCR(r1)
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mtcr r4
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ld r5,_CTR(r1)
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mtctr r5
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ld r6,_XER(r1)
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mtspr SPRN_XER,r6
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ld r7,_DAR(r1)
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mtdar r7
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ld r8,_DSISR(r1)
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mtdsisr r8
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addi r1,r1,SWITCH_FRAME_SIZE /* Unstack our frame */
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ld r0,16(r1) /* get return address */
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mtlr r0
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blr /* return to caller */
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#endif /* CONFIG_PPC_RTAS */
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_GLOBAL(enter_prom)
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mflr r0
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std r0,16(r1)
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stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
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/* Because PROM is running in 32b mode, it clobbers the high order half
|
|
* of all registers that it saves. We therefore save those registers
|
|
* PROM might touch to the stack. (r0, r3-r13 are caller saved)
|
|
*/
|
|
SAVE_GPR(2, r1)
|
|
SAVE_GPR(13, r1)
|
|
SAVE_NVGPRS(r1)
|
|
mfcr r10
|
|
mfmsr r11
|
|
std r10,_CCR(r1)
|
|
std r11,_MSR(r1)
|
|
|
|
/* Put PROM address in SRR0 */
|
|
mtsrr0 r4
|
|
|
|
/* Setup our trampoline return addr in LR */
|
|
bcl 20,31,$+4
|
|
0: mflr r4
|
|
addi r4,r4,(1f - 0b)
|
|
mtlr r4
|
|
|
|
/* Prepare a 32-bit mode big endian MSR
|
|
*/
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
rlwinm r11,r11,0,1,31
|
|
mtsrr1 r11
|
|
rfi
|
|
#else /* CONFIG_PPC_BOOK3E */
|
|
LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_LE)
|
|
andc r11,r11,r12
|
|
mtsrr1 r11
|
|
RFI_TO_KERNEL
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
|
|
|
1: /* Return from OF */
|
|
FIXUP_ENDIAN
|
|
|
|
/* Just make sure that r1 top 32 bits didn't get
|
|
* corrupt by OF
|
|
*/
|
|
rldicl r1,r1,0,32
|
|
|
|
/* Restore the MSR (back to 64 bits) */
|
|
ld r0,_MSR(r1)
|
|
MTMSRD(r0)
|
|
isync
|
|
|
|
/* Restore other registers */
|
|
REST_GPR(2, r1)
|
|
REST_GPR(13, r1)
|
|
REST_NVGPRS(r1)
|
|
ld r4,_CCR(r1)
|
|
mtcr r4
|
|
|
|
addi r1,r1,SWITCH_FRAME_SIZE
|
|
ld r0,16(r1)
|
|
mtlr r0
|
|
blr
|