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We currently use 64bit I/O on the 32bit registers. This works because there are an even number of assert and status registers, so they're only ever accessed in pairs on 64bit boundaries. There are however other reset controllers for audio and video on the JH7100 SoC with only one status register that isn't 64bit aligned so 64bit I/O results in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
14 lines
443 B
C
14 lines
443 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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*/
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#ifndef __RESET_STARFIVE_JH71X0_H
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#define __RESET_STARFIVE_JH71X0_H
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int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
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void __iomem *assert, void __iomem *status,
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const u32 *asserted, unsigned int nr_resets,
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struct module *owner);
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#endif /* __RESET_STARFIVE_JH71X0_H */
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