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587dd448d9
The sprd_div_helper_round_rate() function calls divider_round_rate()
which calls divider_round_rate_parent() which calls
divider_determine_rate(). This call chain converts back and forth from
the rate request structure to make a determine_rate clk_op fit with a
round_rate clk_op. Simplify the code here by directly calling
divider_determine_rate() instead.
This fixes a smatch warning where an unsigned long is compared to less
than zero, which is impossible. This makes sprd_div_helper_round_rate()
unnecessary as well so simply remove it and fold it into the only caller
left.
Reported-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
Closes: https://lore.kernel.org/r/45fdc54e-7ab6-edd6-d55a-473485608473@oracle.com
Cc: Maxime Ripard <maxime@cerno.tech>
Fixes: 302d2f836d ("clk: sprd: composite: Switch to determine_rate")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20230613195443.1555132-1-sboyd@kernel.org
Reviewed-by: Maxime Ripard <mripard@kernel.org>
81 lines
2 KiB
C
81 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Spreadtrum divider clock driver
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//
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// Copyright (C) 2017 Spreadtrum, Inc.
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// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
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#include <linux/clk-provider.h>
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#include "div.h"
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static long sprd_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct sprd_div *cd = hw_to_sprd_div(hw);
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return divider_round_rate(&cd->common.hw, rate, parent_rate, NULL,
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cd->div.width, 0);
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}
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unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
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const struct sprd_div_internal *div,
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unsigned long parent_rate)
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{
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unsigned long val;
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unsigned int reg;
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regmap_read(common->regmap, common->reg, ®);
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val = reg >> div->shift;
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val &= (1 << div->width) - 1;
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return divider_recalc_rate(&common->hw, parent_rate, val, NULL, 0,
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div->width);
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}
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EXPORT_SYMBOL_GPL(sprd_div_helper_recalc_rate);
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static unsigned long sprd_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sprd_div *cd = hw_to_sprd_div(hw);
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return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate);
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}
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int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
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const struct sprd_div_internal *div,
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unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned long val;
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unsigned int reg;
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val = divider_get_val(rate, parent_rate, NULL,
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div->width, 0);
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regmap_read(common->regmap, common->reg, ®);
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reg &= ~GENMASK(div->width + div->shift - 1, div->shift);
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regmap_write(common->regmap, common->reg,
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reg | (val << div->shift));
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return 0;
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}
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EXPORT_SYMBOL_GPL(sprd_div_helper_set_rate);
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static int sprd_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sprd_div *cd = hw_to_sprd_div(hw);
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return sprd_div_helper_set_rate(&cd->common, &cd->div,
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rate, parent_rate);
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}
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const struct clk_ops sprd_div_ops = {
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.recalc_rate = sprd_div_recalc_rate,
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.round_rate = sprd_div_round_rate,
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.set_rate = sprd_div_set_rate,
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};
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EXPORT_SYMBOL_GPL(sprd_div_ops);
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