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4917394e0c
The warning that a clock operation failed is only printed once. However, the function is called for various different clocks. The limit hides the warnings if different clocks are affected by the failures. The clock ops might fail if the firmware that handles the clocks is misconfigured. Therefore, replace the pr_warn_once with pr_debug to allow the user to see all errors if necessary. By default, hide the error messages and let drivers handle the errors. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20220119115434.2042017-1-m.tretter@pengutronix.de Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
143 lines
3.3 KiB
C
143 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Zynq UltraScale+ MPSoC clock controller
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*
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* Copyright (C) 2016-2018 Xilinx
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*
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* Gated clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "clk-zynqmp.h"
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/**
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* struct zynqmp_clk_gate - gating clock
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* @hw: handle between common and hardware-specific interfaces
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* @flags: hardware-specific flags
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* @clk_id: Id of clock
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*/
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struct zynqmp_clk_gate {
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struct clk_hw hw;
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u8 flags;
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u32 clk_id;
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};
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#define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)
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/**
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* zynqmp_clk_gate_enable() - Enable clock
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* @hw: handle between common and hardware-specific interfaces
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*
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* Return: 0 on success else error code
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*/
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static int zynqmp_clk_gate_enable(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int ret;
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ret = zynqmp_pm_clock_enable(clk_id);
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if (ret)
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pr_debug("%s() clock enable failed for %s (id %d), ret = %d\n",
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__func__, clk_name, clk_id, ret);
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return ret;
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}
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/*
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* zynqmp_clk_gate_disable() - Disable clock
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* @hw: handle between common and hardware-specific interfaces
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*/
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static void zynqmp_clk_gate_disable(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int ret;
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ret = zynqmp_pm_clock_disable(clk_id);
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if (ret)
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pr_debug("%s() clock disable failed for %s (id %d), ret = %d\n",
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__func__, clk_name, clk_id, ret);
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}
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/**
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* zynqmp_clk_gate_is_enabled() - Check clock state
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* @hw: handle between common and hardware-specific interfaces
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*
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* Return: 1 if enabled, 0 if disabled else error code
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*/
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static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
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const char *clk_name = clk_hw_get_name(hw);
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u32 clk_id = gate->clk_id;
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int state, ret;
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ret = zynqmp_pm_clock_getstate(clk_id, &state);
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if (ret) {
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pr_debug("%s() clock get state failed for %s, ret = %d\n",
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__func__, clk_name, ret);
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return -EIO;
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}
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return state ? 1 : 0;
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}
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static const struct clk_ops zynqmp_clk_gate_ops = {
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.enable = zynqmp_clk_gate_enable,
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.disable = zynqmp_clk_gate_disable,
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.is_enabled = zynqmp_clk_gate_is_enabled,
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};
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/**
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* zynqmp_clk_register_gate() - Register a gate clock with the clock framework
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* @name: Name of this clock
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* @clk_id: Id of this clock
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* @parents: Name of this clock's parents
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* @num_parents: Number of parents
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* @nodes: Clock topology node
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*
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* Return: clock hardware of the registered clock gate
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*/
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struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
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const char * const *parents,
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u8 num_parents,
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const struct clock_topology *nodes)
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{
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struct zynqmp_clk_gate *gate;
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struct clk_hw *hw;
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int ret;
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struct clk_init_data init;
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/* allocate the gate */
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &zynqmp_clk_gate_ops;
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init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
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init.parent_names = parents;
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init.num_parents = 1;
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/* struct clk_gate assignments */
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gate->flags = nodes->type_flag;
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gate->hw.init = &init;
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gate->clk_id = clk_id;
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hw = &gate->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(gate);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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