linux-stable/drivers/interconnect/qcom/sdx55.h
Manivannan Sadhasivam cbb382c5fb interconnect: qcom: Add SDX55 interconnect provider driver
Add driver for the Qualcomm interconnect buses found in SDX55 based
platforms. The topology consists of several NoCs that are controlled by
a remote processor that collects the aggregated bandwidth for each
master-slave pairs.

Based on SM8250 driver and generated from downstream dts.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210121053254.8355-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2021-01-27 13:11:33 +02:00

70 lines
2.1 KiB
C

/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021, Linaro Ltd.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H
#define __DRIVERS_INTERCONNECT_QCOM_SDX55_H
#define SDX55_MASTER_IPA_CORE 0
#define SDX55_MASTER_LLCC 1
#define SDX55_MASTER_TCU_0 2
#define SDX55_MASTER_SNOC_GC_MEM_NOC 3
#define SDX55_MASTER_AMPSS_M0 4
#define SDX55_MASTER_AUDIO 5
#define SDX55_MASTER_BLSP_1 6
#define SDX55_MASTER_QDSS_BAM 7
#define SDX55_MASTER_QPIC 8
#define SDX55_MASTER_SNOC_CFG 9
#define SDX55_MASTER_SPMI_FETCHER 10
#define SDX55_MASTER_ANOC_SNOC 11
#define SDX55_MASTER_IPA 12
#define SDX55_MASTER_MEM_NOC_SNOC 13
#define SDX55_MASTER_MEM_NOC_PCIE_SNOC 14
#define SDX55_MASTER_CRYPTO_CORE_0 15
#define SDX55_MASTER_EMAC 16
#define SDX55_MASTER_IPA_PCIE 17
#define SDX55_MASTER_PCIE 18
#define SDX55_MASTER_QDSS_ETR 19
#define SDX55_MASTER_SDCC_1 20
#define SDX55_MASTER_USB3 21
#define SDX55_SLAVE_IPA_CORE 22
#define SDX55_SLAVE_EBI_CH0 23
#define SDX55_SLAVE_LLCC 24
#define SDX55_SLAVE_MEM_NOC_SNOC 25
#define SDX55_SLAVE_MEM_NOC_PCIE_SNOC 26
#define SDX55_SLAVE_ANOC_SNOC 27
#define SDX55_SLAVE_SNOC_CFG 28
#define SDX55_SLAVE_EMAC_CFG 29
#define SDX55_SLAVE_USB3 30
#define SDX55_SLAVE_TLMM 31
#define SDX55_SLAVE_SPMI_FETCHER 32
#define SDX55_SLAVE_QDSS_CFG 33
#define SDX55_SLAVE_PDM 34
#define SDX55_SLAVE_SNOC_MEM_NOC_GC 35
#define SDX55_SLAVE_TCSR 36
#define SDX55_SLAVE_CNOC_DDRSS 37
#define SDX55_SLAVE_SPMI_VGI_COEX 38
#define SDX55_SLAVE_QPIC 39
#define SDX55_SLAVE_OCIMEM 40
#define SDX55_SLAVE_IPA_CFG 41
#define SDX55_SLAVE_USB3_PHY_CFG 42
#define SDX55_SLAVE_AOP 43
#define SDX55_SLAVE_BLSP_1 44
#define SDX55_SLAVE_SDCC_1 45
#define SDX55_SLAVE_CNOC_MSS 46
#define SDX55_SLAVE_PCIE_PARF 47
#define SDX55_SLAVE_ECC_CFG 48
#define SDX55_SLAVE_AUDIO 49
#define SDX55_SLAVE_AOSS 51
#define SDX55_SLAVE_PRNG 52
#define SDX55_SLAVE_CRYPTO_0_CFG 53
#define SDX55_SLAVE_TCU 54
#define SDX55_SLAVE_CLK_CTL 55
#define SDX55_SLAVE_IMEM_CFG 56
#define SDX55_SLAVE_SERVICE_SNOC 57
#define SDX55_SLAVE_PCIE_0 58
#define SDX55_SLAVE_QDSS_STM 59
#define SDX55_SLAVE_APPSS 60
#endif