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6baa9b20a6
The conversion of sparc32 to genirq is based on original work done by David S. Miller. Daniel Hellstrom has helped in the conversion and implemented the shutdowm functionality. Marcel van Nies <morcles@gmail.com> has tested this on Sparc Station 20 Test status: sun4c - not tested sun4m,pci - not tested sun4m,sbus - tested (Sparc Classic, Sparc Station 5, Sparc Station 20) sun4d - not tested leon - tested on various combinations of leon boards, including SMP variants generic Introduce use of GENERIC_HARDIRQS and GENERIC_IRQ_SHOW Allocate 64 IRQs - which is enough even for SS2000 Use a table of irq_bucket to maintain uses IRQs irq_bucket is also used to chain several irq's that must be called when the same intrrupt is asserted Use irq_link to link a interrupt source to the irq All plafforms must now supply their own build_device_irq method handler_irq rewriten to use generic irq support floppy Read FLOPPY_IRQ from platform device Use generic request_irq to register the floppy interrupt Rewrote sparc_floppy_irq to use the generic irq support pcic: Introduce irq_chip Store mask in chip_data for use in mask/unmask functions Add build_device_irq for pcic Use pcic_build_device_irq in pci_time_init allocate virtual irqs in pcic_fill_irq sun4c: Introduce irq_chip Store mask in chip_data for use in mask/unmask functions Add build_device_irq for sun4c Use sun4c_build_device_irq in sun4c_init_timers sun4m: Introduce irq_chip Introduce dedicated mask/unmask methods Introduce sun4m_handler_data that allow easy access to necessary data in the mask/unmask functions Add a helper method to enable profile_timer (used from smp) Added sun4m_build_device_irq Use sun4m_build_device_irq in sun4m_init_timers TODO: There is no replacement for smp_rotate that always scheduled next CPU as interrupt target upon an interrupt sun4d: Introduce irq_chip Introduce dedicated mask/unmask methods Introduce sun4d_handler_data that allow easy access to necessary data in mask/unmask fuctions Rewrote sun4d_handler_irq to use generic irq support TODO: The original implmentation of enable/disable had: if (irq < NR_IRQS) return; The new implmentation does not distingush between SBUS and cpu interrupts. I am no sure what is right here. I assume we need to do something for the cpu interrupts. I have not succeeded booting my sun4d box (with or without this patch) and my understanding of this platfrom is limited. So I would be a bit suprised if this works. leon: Introduce irq_chip Store mask in chip_data for use in mask/unmask functions Add build_device_irq for leon Use leon_build_device_irq in leon_init_timers Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Acked-by: Daniel Hellstrom <daniel@gaisler.com> Tested-by: Daniel Hellstrom <daniel@gaisler.com> Tested-by: Marcel van Nies <morcles@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
264 lines
6.3 KiB
C
264 lines
6.3 KiB
C
/*
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* sun4c irq support
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*
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* djhr: Hacked out of irq.c into a CPU dependent version.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
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* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
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*/
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#include <linux/init.h>
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#include <asm/oplib.h>
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#include <asm/timer.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include "irq.h"
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/* Sun4c interrupts are typically laid out as follows:
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*
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* 1 - Software interrupt, SBUS level 1
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* 2 - SBUS level 2
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* 3 - ESP SCSI, SBUS level 3
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* 4 - Software interrupt
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* 5 - Lance ethernet, SBUS level 4
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* 6 - Software interrupt
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* 7 - Graphics card, SBUS level 5
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* 8 - SBUS level 6
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* 9 - SBUS level 7
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* 10 - Counter timer
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* 11 - Floppy
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* 12 - Zilog uart
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* 13 - CS4231 audio
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* 14 - Profiling timer
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* 15 - NMI
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*
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* The interrupt enable bits in the interrupt mask register are
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* really only used to enable/disable the timer interrupts, and
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* for signalling software interrupts. There is also a master
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* interrupt enable bit in this register.
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*
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* Interrupts are enabled by setting the SUN4C_INT_* bits, they
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* are disabled by clearing those bits.
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*/
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/*
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* Bit field defines for the interrupt registers on various
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* Sparc machines.
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*/
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/* The sun4c interrupt register. */
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#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
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#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
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#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
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#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
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#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
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#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
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#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
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/*
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* Pointer to the interrupt enable byte
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* Used by entry.S
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*/
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unsigned char __iomem *interrupt_enable;
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static void sun4c_mask_irq(struct irq_data *data)
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{
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unsigned long mask = (unsigned long)data->chip_data;
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if (mask) {
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unsigned long flags;
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local_irq_save(flags);
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mask = sbus_readb(interrupt_enable) & ~mask;
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sbus_writeb(mask, interrupt_enable);
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local_irq_restore(flags);
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}
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}
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static void sun4c_unmask_irq(struct irq_data *data)
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{
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unsigned long mask = (unsigned long)data->chip_data;
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if (mask) {
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unsigned long flags;
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local_irq_save(flags);
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mask = sbus_readb(interrupt_enable) | mask;
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sbus_writeb(mask, interrupt_enable);
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local_irq_restore(flags);
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}
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}
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static unsigned int sun4c_startup_irq(struct irq_data *data)
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{
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irq_link(data->irq);
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sun4c_unmask_irq(data);
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return 0;
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}
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static void sun4c_shutdown_irq(struct irq_data *data)
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{
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sun4c_mask_irq(data);
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irq_unlink(data->irq);
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}
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static struct irq_chip sun4c_irq = {
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.name = "sun4c",
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.irq_startup = sun4c_startup_irq,
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.irq_shutdown = sun4c_shutdown_irq,
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.irq_mask = sun4c_mask_irq,
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.irq_unmask = sun4c_unmask_irq,
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};
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static unsigned int sun4c_build_device_irq(struct platform_device *op,
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unsigned int real_irq)
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{
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unsigned int irq;
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if (real_irq >= 16) {
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prom_printf("Bogus sun4c IRQ %u\n", real_irq);
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prom_halt();
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}
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irq = irq_alloc(real_irq, real_irq);
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if (irq) {
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unsigned long mask = 0UL;
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switch (real_irq) {
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case 1:
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mask = SUN4C_INT_E1;
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break;
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case 8:
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mask = SUN4C_INT_E8;
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break;
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case 10:
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mask = SUN4C_INT_E10;
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break;
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case 14:
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mask = SUN4C_INT_E14;
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break;
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default:
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/* All the rest are either always enabled,
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* or are for signalling software interrupts.
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*/
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break;
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}
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irq_set_chip_and_handler_name(irq, &sun4c_irq,
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handle_level_irq, "level");
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irq_set_chip_data(irq, (void *)mask);
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}
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return irq;
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}
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struct sun4c_timer_info {
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u32 l10_count;
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u32 l10_limit;
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u32 l14_count;
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u32 l14_limit;
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};
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static struct sun4c_timer_info __iomem *sun4c_timers;
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static void sun4c_clear_clock_irq(void)
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{
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sbus_readl(&sun4c_timers->l10_limit);
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}
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static void sun4c_load_profile_irq(int cpu, unsigned int limit)
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{
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/* Errm.. not sure how to do this.. */
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}
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static void __init sun4c_init_timers(irq_handler_t counter_fn)
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{
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const struct linux_prom_irqs *prom_irqs;
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struct device_node *dp;
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unsigned int irq;
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const u32 *addr;
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int err;
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dp = of_find_node_by_name(NULL, "counter-timer");
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if (!dp) {
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prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
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prom_halt();
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}
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addr = of_get_property(dp, "address", NULL);
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if (!addr) {
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prom_printf("sun4c_init_timers: No address property\n");
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prom_halt();
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}
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sun4c_timers = (void __iomem *) (unsigned long) addr[0];
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prom_irqs = of_get_property(dp, "intr", NULL);
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of_node_put(dp);
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if (!prom_irqs) {
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prom_printf("sun4c_init_timers: No intr property\n");
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prom_halt();
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}
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/* Have the level 10 timer tick at 100HZ. We don't touch the
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* level 14 timer limit since we are letting the prom handle
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* them until we have a real console driver so L1-A works.
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*/
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sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
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master_l10_counter = &sun4c_timers->l10_count;
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irq = sun4c_build_device_irq(NULL, prom_irqs[0].pri);
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err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
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if (err) {
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prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
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prom_halt();
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}
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/* disable timer interrupt */
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sun4c_mask_irq(irq_get_irq_data(irq));
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}
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#ifdef CONFIG_SMP
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static void sun4c_nop(void)
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{
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}
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#endif
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void __init sun4c_init_IRQ(void)
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{
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struct device_node *dp;
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const u32 *addr;
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dp = of_find_node_by_name(NULL, "interrupt-enable");
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if (!dp) {
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prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
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prom_halt();
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}
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addr = of_get_property(dp, "address", NULL);
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of_node_put(dp);
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if (!addr) {
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prom_printf("sun4c_init_IRQ: No address property\n");
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prom_halt();
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}
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interrupt_enable = (void __iomem *) (unsigned long) addr[0];
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BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
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sparc_irq_config.init_timers = sun4c_init_timers;
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sparc_irq_config.build_device_irq = sun4c_build_device_irq;
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#ifdef CONFIG_SMP
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BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
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BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
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BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
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#endif
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sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
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/* Cannot enable interrupts until OBP ticker is disabled. */
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}
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