Biju Das fa2a30f8e0 clk: renesas: rzg2l: Fix clk status function ... As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value 0 means clock is not supplied and 1 means clock is supplied. This patch fixes the issue by removing the inverted logic. Fixing the above, triggered following 2 issues 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK. Fixed this issue by adding these clocks as critical clocks. 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK. So will provide a fix in the DMA driver to turn on DMA_PCLK. Fixes: ef3c613ccd ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210922112405.26413-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>		2021-09-24 15:11:05 +02:00
..
clk-div6.c	clk: renesas: div6: Implement range checking	2021-05-11 09:58:13 +02:00
clk-div6.h	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
clk-emev2.c	Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next	2018-10-18 15:33:52 -07:00
clk-mstp.c	clk: renesas: Zero init clk_init_data	2021-03-30 09:58:27 +02:00
clk-r8a73a4.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-r8a7740.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-r8a7778.c	Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next	2018-10-18 15:33:52 -07:00
clk-r8a7779.c	Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next	2018-10-18 15:33:52 -07:00
clk-rz.c	remove ioremap_nocache and devm_ioremap_nocache	2020-01-06 09:45:59 +01:00
clk-sh73a0.c	clk: renesas: sh73a0: Stop using __raw_*() I/O accessors	2020-12-10 08:34:01 +01:00
Kconfig	clk: renesas: Make CLK_R9A06G032 invisible	2021-08-13 12:05:41 +02:00
Makefile	clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]	2021-07-19 11:22:20 +02:00
r7s9210-cpg-mssr.c	clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag	2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c	clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic	2021-07-19 10:53:52 +02:00
r8a774b1-cpg-mssr.c	clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic	2021-07-19 10:53:52 +02:00
r8a774c0-cpg-mssr.c	clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic	2021-07-19 10:53:52 +02:00
r8a774e1-cpg-mssr.c	clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic	2021-07-19 10:53:52 +02:00
r8a779a0-cpg-mssr.c	clk: renesas: r8a779a0: Add the DSI clocks	2021-07-19 10:53:52 +02:00
r8a7742-cpg-mssr.c	clk: renesas: r8a7742: Add clk entry for VSPR	2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c	clk: renesas: r8a7795: Add TMU clocks	2021-03-12 09:22:46 +01:00
r8a7796-cpg-mssr.c	clk: renesas: r8a7796: Add TMU clocks	2020-12-28 10:45:16 +01:00
r8a77470-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c	clk: renesas: r8a77965: Add DAB clock	2021-03-08 10:30:02 +01:00
r8a77970-cpg-mssr.c	clk: renesas: rcar-gen3: Mark RWDT clocks as critical	2020-06-22 16:53:49 +02:00
r8a77980-cpg-mssr.c	clk: renesas: rcar-gen3: Mark RWDT clocks as critical	2020-06-22 16:53:49 +02:00
r8a77990-cpg-mssr.c	clk: renesas: r8a77990: Add DAB clock	2021-03-08 10:30:02 +01:00
r8a77995-cpg-mssr.c	clk: renesas: r8a77995: Add ZA2 clock	2021-05-27 15:27:28 +02:00
r9a06g032-clocks.c	clk: renesas: r9a06g032: Switch to .determine_rate()	2021-05-11 10:00:40 +02:00
r9a07g044-cpg.c	clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical	2021-09-24 15:11:05 +02:00
rcar-cpg-lib.c	clk: renesas: Zero init clk_init_data	2021-03-30 09:58:27 +02:00
rcar-cpg-lib.h	clk: renesas: rcar-gen3: Factor out CPG library	2021-01-12 12:35:13 +01:00
rcar-gen2-cpg.c	clk: renesas: Zero init clk_init_data	2021-03-30 09:58:27 +02:00
rcar-gen2-cpg.h	clk: renesas: rcar-gen2: Change multipliers and dividers to u8	2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c	clk: renesas: rcar-gen3: Add boost support to Z clocks	2021-05-11 09:57:06 +02:00
rcar-gen3-cpg.h	clk: renesas: r8a774c0: Add RPC clocks	2020-12-10 08:34:01 +01:00
rcar-usb2-clock-sel.c	clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereference	2021-08-28 21:29:36 -07:00
renesas-cpg-mssr.c	clk: renesas: cpg-mssr: Make srstclr[] comment block consistent	2021-05-27 15:27:16 +02:00
renesas-cpg-mssr.h	clk: renesas: cpg-mssr: Add support for R-Car V3U	2020-09-17 15:32:25 +02:00
rzg2l-cpg.c	clk: renesas: rzg2l: Fix clk status function	2021-09-24 15:11:05 +02:00
rzg2l-cpg.h	clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]	2021-07-19 11:22:20 +02:00