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![Xiongfeng Wang](/assets/img/avatar_default.png)
To add SW BOOST support for CPPC, we need to get the max frequency of boost mode and non-boost mode. ACPI spec 6.2 section 8.4.7.1 describes the following two CPC registers. "Highest performance is the absolute maximum performance an individual processor may reach, assuming ideal conditions. This performance level may not be sustainable for long durations, and may only be achievable if other platform components are in a specific state; for example, it may require other processors be in an idle state. Nominal Performance is the maximum sustained performance level of the processor, assuming ideal operating conditions. In absence of an external constraint (power, thermal, etc.) this is the performance level the platform is expected to be able to maintain continuously. All processors are expected to be able to sustain their nominal performance state simultaneously." To add SW BOOST support for CPPC, we can use Highest Performance as the max performance in boost mode and Nominal Performance as the max performance in non-boost mode. If the Highest Performance is greater than the Nominal Performance, we assume SW BOOST is supported. The current CPPC driver does not support SW BOOST and use 'Highest Performance' as the max performance the CPU can achieve. 'Nominal Performance' is used to convert 'performance' to 'frequency'. That means, if firmware enable boost and provide a value for Highest Performance which is greater than Nominal Performance, boost feature is enabled by default. Because SW BOOST is disabled by default, so, after this patch, boost feature is disabled by default even if boost is enabled by firmware. Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Suggested-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> [ rjw: Subject ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
536 lines
13 KiB
C
536 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* CPPC (Collaborative Processor Performance Control) driver for
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* interfacing with the CPUfreq layer and governors. See
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* cppc_acpi.c for CPPC specific methods.
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*
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* (C) Copyright 2014, 2015 Linaro Ltd.
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* Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
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*/
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#define pr_fmt(fmt) "CPPC Cpufreq:" fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/dmi.h>
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#include <linux/time.h>
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#include <linux/vmalloc.h>
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#include <asm/unaligned.h>
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#include <acpi/cppc_acpi.h>
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/* Minimum struct length needed for the DMI processor entry we want */
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#define DMI_ENTRY_PROCESSOR_MIN_LENGTH 48
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/* Offest in the DMI processor structure for the max frequency */
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#define DMI_PROCESSOR_MAX_SPEED 0x14
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/*
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* These structs contain information parsed from per CPU
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* ACPI _CPC structures.
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* e.g. For each CPU the highest, lowest supported
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* performance capabilities, desired performance level
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* requested etc.
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*/
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static struct cppc_cpudata **all_cpu_data;
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static bool boost_supported;
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struct cppc_workaround_oem_info {
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char oem_id[ACPI_OEM_ID_SIZE + 1];
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char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
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u32 oem_revision;
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};
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static bool apply_hisi_workaround;
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static struct cppc_workaround_oem_info wa_info[] = {
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{
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.oem_id = "HISI ",
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.oem_table_id = "HIP07 ",
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.oem_revision = 0,
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}, {
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.oem_id = "HISI ",
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.oem_table_id = "HIP08 ",
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.oem_revision = 0,
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}
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};
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static unsigned int cppc_cpufreq_perf_to_khz(struct cppc_cpudata *cpu,
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unsigned int perf);
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/*
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* HISI platform does not support delivered performance counter and
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* reference performance counter. It can calculate the performance using the
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* platform specific mechanism. We reuse the desired performance register to
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* store the real performance calculated by the platform.
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*/
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static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpunum)
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{
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struct cppc_cpudata *cpudata = all_cpu_data[cpunum];
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u64 desired_perf;
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int ret;
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ret = cppc_get_desired_perf(cpunum, &desired_perf);
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if (ret < 0)
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return -EIO;
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return cppc_cpufreq_perf_to_khz(cpudata, desired_perf);
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}
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static void cppc_check_hisi_workaround(void)
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{
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struct acpi_table_header *tbl;
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acpi_status status = AE_OK;
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int i;
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status = acpi_get_table(ACPI_SIG_PCCT, 0, &tbl);
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if (ACPI_FAILURE(status) || !tbl)
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return;
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for (i = 0; i < ARRAY_SIZE(wa_info); i++) {
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if (!memcmp(wa_info[i].oem_id, tbl->oem_id, ACPI_OEM_ID_SIZE) &&
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!memcmp(wa_info[i].oem_table_id, tbl->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
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wa_info[i].oem_revision == tbl->oem_revision) {
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apply_hisi_workaround = true;
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break;
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}
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}
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acpi_put_table(tbl);
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}
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/* Callback function used to retrieve the max frequency from DMI */
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static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
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{
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const u8 *dmi_data = (const u8 *)dm;
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u16 *mhz = (u16 *)private;
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if (dm->type == DMI_ENTRY_PROCESSOR &&
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dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
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u16 val = (u16)get_unaligned((const u16 *)
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(dmi_data + DMI_PROCESSOR_MAX_SPEED));
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*mhz = val > *mhz ? val : *mhz;
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}
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}
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/* Look up the max frequency in DMI */
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static u64 cppc_get_dmi_max_khz(void)
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{
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u16 mhz = 0;
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dmi_walk(cppc_find_dmi_mhz, &mhz);
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/*
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* Real stupid fallback value, just in case there is no
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* actual value set.
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*/
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mhz = mhz ? mhz : 1;
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return (1000 * mhz);
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}
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/*
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* If CPPC lowest_freq and nominal_freq registers are exposed then we can
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* use them to convert perf to freq and vice versa
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*
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* If the perf/freq point lies between Nominal and Lowest, we can treat
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* (Low perf, Low freq) and (Nom Perf, Nom freq) as 2D co-ordinates of a line
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* and extrapolate the rest
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* For perf/freq > Nominal, we use the ratio perf:freq at Nominal for conversion
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*/
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static unsigned int cppc_cpufreq_perf_to_khz(struct cppc_cpudata *cpu,
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unsigned int perf)
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{
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static u64 max_khz;
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struct cppc_perf_caps *caps = &cpu->perf_caps;
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u64 mul, div;
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if (caps->lowest_freq && caps->nominal_freq) {
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if (perf >= caps->nominal_perf) {
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mul = caps->nominal_freq;
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div = caps->nominal_perf;
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} else {
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mul = caps->nominal_freq - caps->lowest_freq;
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div = caps->nominal_perf - caps->lowest_perf;
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}
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} else {
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if (!max_khz)
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max_khz = cppc_get_dmi_max_khz();
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mul = max_khz;
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div = cpu->perf_caps.highest_perf;
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}
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return (u64)perf * mul / div;
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}
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static unsigned int cppc_cpufreq_khz_to_perf(struct cppc_cpudata *cpu,
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unsigned int freq)
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{
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static u64 max_khz;
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struct cppc_perf_caps *caps = &cpu->perf_caps;
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u64 mul, div;
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if (caps->lowest_freq && caps->nominal_freq) {
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if (freq >= caps->nominal_freq) {
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mul = caps->nominal_perf;
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div = caps->nominal_freq;
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} else {
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mul = caps->lowest_perf;
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div = caps->lowest_freq;
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}
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} else {
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if (!max_khz)
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max_khz = cppc_get_dmi_max_khz();
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mul = cpu->perf_caps.highest_perf;
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div = max_khz;
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}
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return (u64)freq * mul / div;
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}
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static int cppc_cpufreq_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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struct cppc_cpudata *cpu;
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struct cpufreq_freqs freqs;
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u32 desired_perf;
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int ret = 0;
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cpu = all_cpu_data[policy->cpu];
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desired_perf = cppc_cpufreq_khz_to_perf(cpu, target_freq);
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/* Return if it is exactly the same perf */
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if (desired_perf == cpu->perf_ctrls.desired_perf)
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return ret;
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cpu->perf_ctrls.desired_perf = desired_perf;
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freqs.old = policy->cur;
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freqs.new = target_freq;
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cpufreq_freq_transition_begin(policy, &freqs);
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ret = cppc_set_perf(cpu->cpu, &cpu->perf_ctrls);
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cpufreq_freq_transition_end(policy, &freqs, ret != 0);
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if (ret)
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pr_debug("Failed to set target on CPU:%d. ret:%d\n",
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cpu->cpu, ret);
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return ret;
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}
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static int cppc_verify_policy(struct cpufreq_policy_data *policy)
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{
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cpufreq_verify_within_cpu_limits(policy);
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return 0;
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}
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static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy)
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{
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int cpu_num = policy->cpu;
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struct cppc_cpudata *cpu = all_cpu_data[cpu_num];
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int ret;
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cpu->perf_ctrls.desired_perf = cpu->perf_caps.lowest_perf;
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ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls);
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if (ret)
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pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n",
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cpu->perf_caps.lowest_perf, cpu_num, ret);
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}
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/*
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* The PCC subspace describes the rate at which platform can accept commands
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* on the shared PCC channel (including READs which do not count towards freq
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* trasition requests), so ideally we need to use the PCC values as a fallback
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* if we don't have a platform specific transition_delay_us
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*/
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#ifdef CONFIG_ARM64
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#include <asm/cputype.h>
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static unsigned int cppc_cpufreq_get_transition_delay_us(int cpu)
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{
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unsigned long implementor = read_cpuid_implementor();
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unsigned long part_num = read_cpuid_part_number();
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unsigned int delay_us = 0;
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switch (implementor) {
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case ARM_CPU_IMP_QCOM:
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switch (part_num) {
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case QCOM_CPU_PART_FALKOR_V1:
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case QCOM_CPU_PART_FALKOR:
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delay_us = 10000;
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break;
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default:
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delay_us = cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
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break;
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}
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break;
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default:
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delay_us = cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
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break;
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}
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return delay_us;
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}
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#else
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static unsigned int cppc_cpufreq_get_transition_delay_us(int cpu)
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{
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return cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
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}
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#endif
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static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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struct cppc_cpudata *cpu;
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unsigned int cpu_num = policy->cpu;
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int ret = 0;
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cpu = all_cpu_data[policy->cpu];
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cpu->cpu = cpu_num;
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ret = cppc_get_perf_caps(policy->cpu, &cpu->perf_caps);
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if (ret) {
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pr_debug("Err reading CPU%d perf capabilities. ret:%d\n",
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cpu_num, ret);
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return ret;
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}
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/* Convert the lowest and nominal freq from MHz to KHz */
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cpu->perf_caps.lowest_freq *= 1000;
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cpu->perf_caps.nominal_freq *= 1000;
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/*
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* Set min to lowest nonlinear perf to avoid any efficiency penalty (see
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* Section 8.4.7.1.1.5 of ACPI 6.1 spec)
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*/
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policy->min = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_nonlinear_perf);
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policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf);
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/*
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* Set cpuinfo.min_freq to Lowest to make the full range of performance
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* available if userspace wants to use any perf between lowest & lowest
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* nonlinear perf
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*/
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policy->cpuinfo.min_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_perf);
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policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf);
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policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu_num);
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policy->shared_type = cpu->shared_type;
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if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
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int i;
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cpumask_copy(policy->cpus, cpu->shared_cpu_map);
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for_each_cpu(i, policy->cpus) {
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if (unlikely(i == policy->cpu))
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continue;
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memcpy(&all_cpu_data[i]->perf_caps, &cpu->perf_caps,
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sizeof(cpu->perf_caps));
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}
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} else if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL) {
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/* Support only SW_ANY for now. */
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pr_debug("Unsupported CPU co-ord type\n");
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return -EFAULT;
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}
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cpu->cur_policy = policy;
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/*
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* If 'highest_perf' is greater than 'nominal_perf', we assume CPU Boost
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* is supported.
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*/
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if (cpu->perf_caps.highest_perf > cpu->perf_caps.nominal_perf)
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boost_supported = true;
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/* Set policy->cur to max now. The governors will adjust later. */
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policy->cur = cppc_cpufreq_perf_to_khz(cpu,
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cpu->perf_caps.highest_perf);
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cpu->perf_ctrls.desired_perf = cpu->perf_caps.highest_perf;
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ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls);
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if (ret)
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pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n",
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cpu->perf_caps.highest_perf, cpu_num, ret);
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return ret;
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}
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static inline u64 get_delta(u64 t1, u64 t0)
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{
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if (t1 > t0 || t0 > ~(u32)0)
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return t1 - t0;
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return (u32)t1 - (u32)t0;
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}
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static int cppc_get_rate_from_fbctrs(struct cppc_cpudata *cpu,
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struct cppc_perf_fb_ctrs fb_ctrs_t0,
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struct cppc_perf_fb_ctrs fb_ctrs_t1)
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{
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u64 delta_reference, delta_delivered;
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u64 reference_perf, delivered_perf;
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reference_perf = fb_ctrs_t0.reference_perf;
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delta_reference = get_delta(fb_ctrs_t1.reference,
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fb_ctrs_t0.reference);
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delta_delivered = get_delta(fb_ctrs_t1.delivered,
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fb_ctrs_t0.delivered);
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/* Check to avoid divide-by zero */
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if (delta_reference || delta_delivered)
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delivered_perf = (reference_perf * delta_delivered) /
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delta_reference;
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else
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delivered_perf = cpu->perf_ctrls.desired_perf;
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return cppc_cpufreq_perf_to_khz(cpu, delivered_perf);
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}
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static unsigned int cppc_cpufreq_get_rate(unsigned int cpunum)
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{
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struct cppc_perf_fb_ctrs fb_ctrs_t0 = {0}, fb_ctrs_t1 = {0};
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struct cppc_cpudata *cpu = all_cpu_data[cpunum];
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int ret;
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if (apply_hisi_workaround)
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return hisi_cppc_cpufreq_get_rate(cpunum);
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ret = cppc_get_perf_ctrs(cpunum, &fb_ctrs_t0);
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if (ret)
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return ret;
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udelay(2); /* 2usec delay between sampling */
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ret = cppc_get_perf_ctrs(cpunum, &fb_ctrs_t1);
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if (ret)
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return ret;
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return cppc_get_rate_from_fbctrs(cpu, fb_ctrs_t0, fb_ctrs_t1);
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}
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static int cppc_cpufreq_set_boost(struct cpufreq_policy *policy, int state)
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{
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struct cppc_cpudata *cpudata;
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int ret;
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if (!boost_supported) {
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pr_err("BOOST not supported by CPU or firmware\n");
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return -EINVAL;
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}
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cpudata = all_cpu_data[policy->cpu];
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if (state)
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policy->max = cppc_cpufreq_perf_to_khz(cpudata,
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cpudata->perf_caps.highest_perf);
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else
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policy->max = cppc_cpufreq_perf_to_khz(cpudata,
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cpudata->perf_caps.nominal_perf);
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policy->cpuinfo.max_freq = policy->max;
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ret = freq_qos_update_request(policy->max_freq_req, policy->max);
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if (ret < 0)
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return ret;
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return 0;
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}
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static struct cpufreq_driver cppc_cpufreq_driver = {
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.flags = CPUFREQ_CONST_LOOPS,
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.verify = cppc_verify_policy,
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.target = cppc_cpufreq_set_target,
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.get = cppc_cpufreq_get_rate,
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.init = cppc_cpufreq_cpu_init,
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.stop_cpu = cppc_cpufreq_stop_cpu,
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.set_boost = cppc_cpufreq_set_boost,
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.name = "cppc_cpufreq",
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};
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static int __init cppc_cpufreq_init(void)
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{
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int i, ret = 0;
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struct cppc_cpudata *cpu;
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if (acpi_disabled)
|
|
return -ENODEV;
|
|
|
|
all_cpu_data = kcalloc(num_possible_cpus(), sizeof(void *),
|
|
GFP_KERNEL);
|
|
if (!all_cpu_data)
|
|
return -ENOMEM;
|
|
|
|
for_each_possible_cpu(i) {
|
|
all_cpu_data[i] = kzalloc(sizeof(struct cppc_cpudata), GFP_KERNEL);
|
|
if (!all_cpu_data[i])
|
|
goto out;
|
|
|
|
cpu = all_cpu_data[i];
|
|
if (!zalloc_cpumask_var(&cpu->shared_cpu_map, GFP_KERNEL))
|
|
goto out;
|
|
}
|
|
|
|
ret = acpi_get_psd_map(all_cpu_data);
|
|
if (ret) {
|
|
pr_debug("Error parsing PSD data. Aborting cpufreq registration.\n");
|
|
goto out;
|
|
}
|
|
|
|
cppc_check_hisi_workaround();
|
|
|
|
ret = cpufreq_register_driver(&cppc_cpufreq_driver);
|
|
if (ret)
|
|
goto out;
|
|
|
|
return ret;
|
|
|
|
out:
|
|
for_each_possible_cpu(i) {
|
|
cpu = all_cpu_data[i];
|
|
if (!cpu)
|
|
break;
|
|
free_cpumask_var(cpu->shared_cpu_map);
|
|
kfree(cpu);
|
|
}
|
|
|
|
kfree(all_cpu_data);
|
|
return -ENODEV;
|
|
}
|
|
|
|
static void __exit cppc_cpufreq_exit(void)
|
|
{
|
|
struct cppc_cpudata *cpu;
|
|
int i;
|
|
|
|
cpufreq_unregister_driver(&cppc_cpufreq_driver);
|
|
|
|
for_each_possible_cpu(i) {
|
|
cpu = all_cpu_data[i];
|
|
free_cpumask_var(cpu->shared_cpu_map);
|
|
kfree(cpu);
|
|
}
|
|
|
|
kfree(all_cpu_data);
|
|
}
|
|
|
|
module_exit(cppc_cpufreq_exit);
|
|
MODULE_AUTHOR("Ashwin Chaugule");
|
|
MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
late_initcall(cppc_cpufreq_init);
|
|
|
|
static const struct acpi_device_id cppc_acpi_ids[] __used = {
|
|
{ACPI_PROCESSOR_DEVICE_HID, },
|
|
{}
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(acpi, cppc_acpi_ids);
|