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![Maxime Ripard](/assets/img/avatar_default.png)
The Allwinner A31 that uses this timer has the timer IP asserted in reset. Add an optional reset property to the DT, and deassert the timer from reset if it's there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
198 lines
5.1 KiB
C
198 lines
5.1 KiB
C
/*
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* Allwinner SoCs hstimer driver.
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*
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* Copyright (C) 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/reset.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_EN(val) BIT(val)
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#define TIMER_IRQ_ST_REG 0x04
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#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
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#define TIMER_CTL_ENABLE BIT(0)
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#define TIMER_CTL_RELOAD BIT(1)
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#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
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#define TIMER_CTL_ONESHOT BIT(7)
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#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
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#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
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#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
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#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
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#define TIMER_SYNC_TICKS 3
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static void __iomem *timer_base;
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static u32 ticks_per_jiffy;
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/*
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* When we disable a timer, we need to wait at least for 2 cycles of
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* the timer source clock. We will use for that the clocksource timer
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* that is already setup and runs at the same frequency than the other
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* timers, and we never will be disabled.
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*/
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static void sun5i_clkevt_sync(void)
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{
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u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
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while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
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cpu_relax();
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}
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static void sun5i_clkevt_time_stop(u8 timer)
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{
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u32 val = readl(timer_base + TIMER_CTL_REG(timer));
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writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
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sun5i_clkevt_sync();
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}
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static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
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{
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writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
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}
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static void sun5i_clkevt_time_start(u8 timer, bool periodic)
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{
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u32 val = readl(timer_base + TIMER_CTL_REG(timer));
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if (periodic)
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val &= ~TIMER_CTL_ONESHOT;
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else
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val |= TIMER_CTL_ONESHOT;
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writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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timer_base + TIMER_CTL_REG(timer));
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}
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static void sun5i_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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sun5i_clkevt_time_stop(0);
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sun5i_clkevt_time_setup(0, ticks_per_jiffy);
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sun5i_clkevt_time_start(0, true);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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sun5i_clkevt_time_stop(0);
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sun5i_clkevt_time_start(0, false);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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sun5i_clkevt_time_stop(0);
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break;
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}
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}
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static int sun5i_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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sun5i_clkevt_time_stop(0);
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sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
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sun5i_clkevt_time_start(0, false);
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return 0;
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}
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static struct clock_event_device sun5i_clockevent = {
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.name = "sun5i_tick",
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.rating = 340,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = sun5i_clkevt_mode,
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.set_next_event = sun5i_clkevt_next_event,
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};
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static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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writel(0x1, timer_base + TIMER_IRQ_ST_REG);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction sun5i_timer_irq = {
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.name = "sun5i_timer0",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sun5i_timer_interrupt,
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.dev_id = &sun5i_clockevent,
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};
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static u64 sun5i_timer_sched_read(void)
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{
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return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
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}
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static void __init sun5i_timer_init(struct device_node *node)
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{
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struct reset_control *rstc;
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unsigned long rate;
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struct clk *clk;
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int ret, irq;
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u32 val;
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timer_base = of_iomap(node, 0);
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if (!timer_base)
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panic("Can't map registers");
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0)
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panic("Can't parse IRQ");
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk))
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panic("Can't get timer clock");
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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rstc = of_reset_control_get(node, NULL);
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if (!IS_ERR(rstc))
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reset_control_deassert(rstc);
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writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
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writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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timer_base + TIMER_CTL_REG(1));
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sched_clock_register(sun5i_timer_sched_read, 32, rate);
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clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
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rate, 340, 32, clocksource_mmio_readl_down);
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ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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ret = setup_irq(irq, &sun5i_timer_irq);
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if (ret)
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pr_warn("failed to setup irq %d\n", irq);
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/* Enable timer0 interrupt */
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val = readl(timer_base + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
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sun5i_clockevent.cpumask = cpu_possible_mask;
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sun5i_clockevent.irq = irq;
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clockevents_config_and_register(&sun5i_clockevent, rate,
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TIMER_SYNC_TICKS, 0xffffffff);
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}
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CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
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sun5i_timer_init);
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CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
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sun5i_timer_init);
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