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![Linus Torvalds](/assets/img/avatar_default.png)
Enumeration - Check Vendor ID only for Config Request Retry Status (Rajat Jain) - Enable Config Request Retry Status when supported (Rajat Jain) - Add generic domain handling (Catalin Marinas) - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado) Resource management - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu) - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr) PCI device hotplug - Prevent NULL dereference during pciehp probe (Andreas Noever) - Move _HPP & _HPX handling into core (Bjorn Helgaas) - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas) - Apply _HPP/_HPX to display devices (Bjorn Helgaas) - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas) - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas) - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas) - Fix wait time in pciehp timeout message (Yinghai Lu) - Add more pciehp Slot Control debug output (Yinghai Lu) - Stop disabling pciehp notifications during init (Yinghai Lu) MSI - Remove arch_msi_check_device() (Alexander Gordeev) - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev) - Move D0 check into pci_msi_check_device() (Alexander Gordeev) - Remove unused kobject from struct msi_desc (Yijing Wang) - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang) - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang) - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang) - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang) - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang) Power management - Drop unused runtime PM support code for PCIe ports (Rafael J. Wysocki) - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki) AER - Add additional AER error strings (Gong Chen) - Make <linux/aer.h> standalone includable (Thierry Reding) Virtualization - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson) - Add ACS quirk for Intel 10G NICs (Alex Williamson) - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp) - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson) - Add device flag helpers (Ethan Zhao) - Assume all Mellanox devices have broken INTx masking (Gavin Shan) Generic host bridge driver - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau) - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau) - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau) - Fix the conversion of IO ranges into IO resources (Liviu Dudau) - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau) - Add support for parsing PCI host bridge resources from DT (Liviu Dudau) - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau) - Add arm64 architectural support for PCI (Liviu Dudau) APM X-Gene - Add APM X-Gene PCIe driver (Tanmay Inamdar) - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar) Freescale i.MX6 - Probe in module_init(), not fs_initcall() (Lucas Stach) - Delay enabling reference clock for SS until it stabilizes (Tim Harvey) Marvell MVEBU - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni) NVIDIA Tegra - Make sure the PCIe PLL is really reset (Eric Yuen) - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang) - Fix extended configuration space mapping (Peter Daifuku) - Implement resource hierarchy (Thierry Reding) - Clear CLKREQ# enable on port disable (Thierry Reding) - Add Tegra124 support (Thierry Reding) ST Microelectronics SPEAr13xx - Pass config resource through reg property (Pratyush Anand) Synopsys DesignWare - Use NULL instead of false (Fabio Estevam) - Parse bus-range property from devicetree (Lucas Stach) - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach) - Remove pci_assign_unassigned_resources() (Lucas Stach) - Check private_data validity in single place (Lucas Stach) - Setup and clear exactly one MSI at a time (Lucas Stach) - Remove open-coded bitmap operations (Lucas Stach) - Fix configuration base address when using 'reg' (Minghuan Lian) - Fix IO resource end address calculation (Minghuan Lian) - Rename get_msi_data() to get_msi_addr() (Minghuan Lian) - Add get_msi_data() to pcie_host_ops (Minghuan Lian) - Add support for v3.65 hardware (Murali Karicheri) - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand) TI Keystone - Add TI Keystone PCIe driver (Murali Karicheri) - Limit MRSS for all downstream devices (Murali Karicheri) - Assume controller is already in RC mode (Murali Karicheri) - Set device ID based on SoC to support multiple ports (Murali Karicheri) Xilinx AXI - Add Xilinx AXI PCIe driver (Srikanth Thokala) - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter) Miscellaneous - Clean up whitespace (Quentin Lambert) - Remove assignments from "if" conditions (Quentin Lambert) - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri) - x86: Mark DMI tables as initialization data (Mathias Krause) - x86: Move __init annotation to the correct place (Mathias Krause) - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause) - x86: Constify pci_mmcfg_probes[] array (Mathias Krause) - x86: Mark PCI BIOS initialization code as such (Mathias Krause) - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya) - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUNWmJAAoJEFmIoMA60/r8GncP/3uHRoBrnaF6pv+S1l1p3Fs/ l1kKH91/IuAAU7VJX8pkNybFqx02topWmiVVXAzqvD01PcRLGCLjPbWl5h+y5/Ja CHZH33AwHAmm0kt4BrOSOeHTLJhAigly2zV3P4F8jRIgyaeMoGZ6Ko4tkQUpm21k +ohrOd4cxYkmzzCjKwsZZhKnyRNpae8FmTk3VQBPuN8DbhvFPrqo5/+GeAdSZTdS HZHpfl2HL4095aY7uBVsZqNkjQyl6SnWwjkjLnuI8q3qA3BLgDZE/Jr8F/MNuW1V y01JIjerFWMDFyBIkpg7moYnODy6oP3KvczwYdKGmqsJja+0MQvYhLTwD+R/yTQS SewJA0mL3T3EJEfnFYkCiaIX27xIwk/FxHfaKPN91xgx/QM7xCVZNrU2/dXjhoX1 GqLKxOEaFHhWWTyT5Dj27I0ZcElzFZ3tIwvrHfs8y22oAuAlsAypaUgvUwRfL4CO hOj4ITZa0t041sYWqxCoGAA9Fdp8HMzNKKS5F4mhADz4Ad9v6uPCNv/s/RoxVsbm jhZOtPYJ0/iCA+kNVX563S8Z3VpfPI+7bBjcj2WKdzW+IlICvOKT+kvwL2Tv/rE7 w0hrNsbkgGsYbPldMx7LwCavsUtYFuNj0zoU6vkhP2jk6O2Tn5VXDmjrXH0v3iHI v03vlUtre0bQ26fzDyLQ =4Zv1 -----END PGP SIGNATURE----- Merge tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "The interesting things here are: - Turn on Config Request Retry Status Software Visibility. This caused hangs last time, but we included a fix this time. - Rework PCI device configuration to use _HPP/_HPX more aggressively - Allow PCI devices to be put into D3cold during system suspend - Add arm64 PCI support - Add APM X-Gene host bridge driver - Add TI Keystone host bridge driver - Add Xilinx AXI host bridge driver More detailed summary: Enumeration - Check Vendor ID only for Config Request Retry Status (Rajat Jain) - Enable Config Request Retry Status when supported (Rajat Jain) - Add generic domain handling (Catalin Marinas) - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado) Resource management - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu) - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr) PCI device hotplug - Prevent NULL dereference during pciehp probe (Andreas Noever) - Move _HPP & _HPX handling into core (Bjorn Helgaas) - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas) - Apply _HPP/_HPX to display devices (Bjorn Helgaas) - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas) - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas) - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas) - Fix wait time in pciehp timeout message (Yinghai Lu) - Add more pciehp Slot Control debug output (Yinghai Lu) - Stop disabling pciehp notifications during init (Yinghai Lu) MSI - Remove arch_msi_check_device() (Alexander Gordeev) - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev) - Move D0 check into pci_msi_check_device() (Alexander Gordeev) - Remove unused kobject from struct msi_desc (Yijing Wang) - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang) - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang) - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang) - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang) - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang) Power management - Drop unused runtime PM support code for PCIe ports (Rafael J. Wysocki) - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki) AER - Add additional AER error strings (Gong Chen) - Make <linux/aer.h> standalone includable (Thierry Reding) Virtualization - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson) - Add ACS quirk for Intel 10G NICs (Alex Williamson) - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp) - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson) - Add device flag helpers (Ethan Zhao) - Assume all Mellanox devices have broken INTx masking (Gavin Shan) Generic host bridge driver - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau) - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau) - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau) - Fix the conversion of IO ranges into IO resources (Liviu Dudau) - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau) - Add support for parsing PCI host bridge resources from DT (Liviu Dudau) - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau) - Add arm64 architectural support for PCI (Liviu Dudau) APM X-Gene - Add APM X-Gene PCIe driver (Tanmay Inamdar) - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar) Freescale i.MX6 - Probe in module_init(), not fs_initcall() (Lucas Stach) - Delay enabling reference clock for SS until it stabilizes (Tim Harvey) Marvell MVEBU - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni) NVIDIA Tegra - Make sure the PCIe PLL is really reset (Eric Yuen) - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang) - Fix extended configuration space mapping (Peter Daifuku) - Implement resource hierarchy (Thierry Reding) - Clear CLKREQ# enable on port disable (Thierry Reding) - Add Tegra124 support (Thierry Reding) ST Microelectronics SPEAr13xx - Pass config resource through reg property (Pratyush Anand) Synopsys DesignWare - Use NULL instead of false (Fabio Estevam) - Parse bus-range property from devicetree (Lucas Stach) - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach) - Remove pci_assign_unassigned_resources() (Lucas Stach) - Check private_data validity in single place (Lucas Stach) - Setup and clear exactly one MSI at a time (Lucas Stach) - Remove open-coded bitmap operations (Lucas Stach) - Fix configuration base address when using 'reg' (Minghuan Lian) - Fix IO resource end address calculation (Minghuan Lian) - Rename get_msi_data() to get_msi_addr() (Minghuan Lian) - Add get_msi_data() to pcie_host_ops (Minghuan Lian) - Add support for v3.65 hardware (Murali Karicheri) - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand) TI Keystone - Add TI Keystone PCIe driver (Murali Karicheri) - Limit MRSS for all downstream devices (Murali Karicheri) - Assume controller is already in RC mode (Murali Karicheri) - Set device ID based on SoC to support multiple ports (Murali Karicheri) Xilinx AXI - Add Xilinx AXI PCIe driver (Srikanth Thokala) - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter) Miscellaneous - Clean up whitespace (Quentin Lambert) - Remove assignments from "if" conditions (Quentin Lambert) - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri) - x86: Mark DMI tables as initialization data (Mathias Krause) - x86: Move __init annotation to the correct place (Mathias Krause) - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause) - x86: Constify pci_mmcfg_probes[] array (Mathias Krause) - x86: Mark PCI BIOS initialization code as such (Mathias Krause) - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya) - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser)" * tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (109 commits) arm64: dts: Add APM X-Gene PCIe device tree nodes PCI: Add ACS quirk for AMD A88X southbridge devices PCI: xgene: Add APM X-Gene PCIe driver PCI: designware: Remove open-coded bitmap operations PCI/MSI: Remove unnecessary temporary variable PCI/MSI: Use __write_msi_msg() instead of write_msi_msg() MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg() PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg() PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib PCI/MSI: Remove unused kobject from struct msi_desc PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported() PCI/MSI: Move D0 check into pci_msi_check_device() PCI/MSI: Remove arch_msi_check_device() irqchip: armada-370-xp: Remove arch_msi_check_device() PCI/MSI/PPC: Remove arch_msi_check_device() arm64: Add architectural support for PCI PCI: Add pci_remap_iospace() to map bus I/O resources of/pci: Add support for parsing PCI host bridge resources from DT of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr() ... Conflicts: arch/arm64/boot/dts/apm-storm.dtsi
536 lines
13 KiB
C
536 lines
13 KiB
C
/*
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* Marvell Armada 370 and Armada XP SoC IRQ handling
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/cpu.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/irqdomain.h>
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#include <linux/slab.h>
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#include <linux/msi.h>
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#include <asm/mach/arch.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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/* Interrupt Controller Registers Map */
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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#define ARMADA_370_XP_INT_CONTROL (0x00)
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#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
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#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
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#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
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#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
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#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
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#define ARMADA_375_PPI_CAUSE (0x10)
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#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
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#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
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#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
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#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
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#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
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#define IPI_DOORBELL_START (0)
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#define IPI_DOORBELL_END (8)
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#define IPI_DOORBELL_MASK 0xFF
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#define PCI_MSI_DOORBELL_START (16)
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#define PCI_MSI_DOORBELL_NR (16)
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#define PCI_MSI_DOORBELL_END (32)
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#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
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static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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#ifdef CONFIG_PCI_MSI
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static struct irq_domain *armada_370_xp_msi_domain;
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static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
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static DEFINE_MUTEX(msi_used_lock);
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static phys_addr_t msi_doorbell_addr;
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#endif
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/*
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* In SMP mode:
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* For shared global interrupts, mask/unmask global enable bit
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* For CPU interrupts, mask/unmask the calling CPU's bit
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*/
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static void armada_370_xp_irq_mask(struct irq_data *d)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_SET_MASK_OFFS);
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}
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static void armada_370_xp_irq_unmask(struct irq_data *d)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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#ifdef CONFIG_PCI_MSI
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static int armada_370_xp_alloc_msi(void)
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{
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int hwirq;
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mutex_lock(&msi_used_lock);
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hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
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if (hwirq >= PCI_MSI_DOORBELL_NR)
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hwirq = -ENOSPC;
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else
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set_bit(hwirq, msi_used);
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mutex_unlock(&msi_used_lock);
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return hwirq;
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}
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static void armada_370_xp_free_msi(int hwirq)
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{
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mutex_lock(&msi_used_lock);
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if (!test_bit(hwirq, msi_used))
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pr_err("trying to free unused MSI#%d\n", hwirq);
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else
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clear_bit(hwirq, msi_used);
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mutex_unlock(&msi_used_lock);
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}
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static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
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struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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struct msi_msg msg;
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int virq, hwirq;
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/* We support MSI, but not MSI-X */
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if (desc->msi_attrib.is_msix)
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return -EINVAL;
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hwirq = armada_370_xp_alloc_msi();
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if (hwirq < 0)
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return hwirq;
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virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
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if (!virq) {
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armada_370_xp_free_msi(hwirq);
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return -EINVAL;
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}
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irq_set_msi_desc(virq, desc);
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msg.address_lo = msi_doorbell_addr;
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msg.address_hi = 0;
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msg.data = 0xf00 | (hwirq + 16);
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write_msi_msg(virq, &msg);
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return 0;
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}
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static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
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unsigned int irq)
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{
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struct irq_data *d = irq_get_irq_data(irq);
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unsigned long hwirq = d->hwirq;
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irq_dispose_mapping(irq);
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armada_370_xp_free_msi(hwirq);
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}
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static struct irq_chip armada_370_xp_msi_irq_chip = {
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.name = "armada_370_xp_msi_irq",
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.irq_enable = unmask_msi_irq,
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.irq_disable = mask_msi_irq,
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.irq_mask = mask_msi_irq,
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.irq_unmask = unmask_msi_irq,
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};
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static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
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handle_simple_irq);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
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.map = armada_370_xp_msi_map,
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};
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static int armada_370_xp_msi_init(struct device_node *node,
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phys_addr_t main_int_phys_base)
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{
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struct msi_chip *msi_chip;
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u32 reg;
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int ret;
|
|
|
|
msi_doorbell_addr = main_int_phys_base +
|
|
ARMADA_370_XP_SW_TRIG_INT_OFFS;
|
|
|
|
msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
|
|
if (!msi_chip)
|
|
return -ENOMEM;
|
|
|
|
msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
|
|
msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
|
|
msi_chip->of_node = node;
|
|
|
|
armada_370_xp_msi_domain =
|
|
irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
|
|
&armada_370_xp_msi_irq_ops,
|
|
NULL);
|
|
if (!armada_370_xp_msi_domain) {
|
|
kfree(msi_chip);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = of_pci_msi_chip_add(msi_chip);
|
|
if (ret < 0) {
|
|
irq_domain_remove(armada_370_xp_msi_domain);
|
|
kfree(msi_chip);
|
|
return ret;
|
|
}
|
|
|
|
reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
|
|
| PCI_MSI_DOORBELL_MASK;
|
|
|
|
writel(reg, per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
|
|
/* Unmask IPI interrupt */
|
|
writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static inline int armada_370_xp_msi_init(struct device_node *node,
|
|
phys_addr_t main_int_phys_base)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMP
|
|
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
|
|
|
|
static int armada_xp_set_affinity(struct irq_data *d,
|
|
const struct cpumask *mask_val, bool force)
|
|
{
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
|
unsigned long reg, mask;
|
|
int cpu;
|
|
|
|
/* Select a single core from the affinity mask which is online */
|
|
cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
|
mask = 1UL << cpu_logical_map(cpu);
|
|
|
|
raw_spin_lock(&irq_controller_lock);
|
|
reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
|
|
reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
|
|
writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
|
|
raw_spin_unlock(&irq_controller_lock);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static struct irq_chip armada_370_xp_irq_chip = {
|
|
.name = "armada_370_xp_irq",
|
|
.irq_mask = armada_370_xp_irq_mask,
|
|
.irq_mask_ack = armada_370_xp_irq_mask,
|
|
.irq_unmask = armada_370_xp_irq_unmask,
|
|
#ifdef CONFIG_SMP
|
|
.irq_set_affinity = armada_xp_set_affinity,
|
|
#endif
|
|
};
|
|
|
|
static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
|
|
unsigned int virq, irq_hw_number_t hw)
|
|
{
|
|
armada_370_xp_irq_mask(irq_get_irq_data(virq));
|
|
if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
|
|
writel(hw, per_cpu_int_base +
|
|
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
else
|
|
writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
|
irq_set_status_flags(virq, IRQ_LEVEL);
|
|
|
|
if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
|
|
irq_set_percpu_devid(virq);
|
|
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
|
|
handle_percpu_devid_irq);
|
|
|
|
} else {
|
|
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
|
|
handle_level_irq);
|
|
}
|
|
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
static void armada_mpic_send_doorbell(const struct cpumask *mask,
|
|
unsigned int irq)
|
|
{
|
|
int cpu;
|
|
unsigned long map = 0;
|
|
|
|
/* Convert our logical CPU mask into a physical one. */
|
|
for_each_cpu(cpu, mask)
|
|
map |= 1 << cpu_logical_map(cpu);
|
|
|
|
/*
|
|
* Ensure that stores to Normal memory are visible to the
|
|
* other CPUs before issuing the IPI.
|
|
*/
|
|
dsb();
|
|
|
|
/* submit softirq */
|
|
writel((map << 8) | irq, main_int_base +
|
|
ARMADA_370_XP_SW_TRIG_INT_OFFS);
|
|
}
|
|
|
|
static void armada_xp_mpic_smp_cpu_init(void)
|
|
{
|
|
u32 control;
|
|
int nr_irqs, i;
|
|
|
|
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
|
|
nr_irqs = (control >> 2) & 0x3ff;
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
|
|
|
|
/* Clear pending IPIs */
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
/* Enable first 8 IPIs */
|
|
writel(IPI_DOORBELL_MASK, per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
|
|
/* Unmask IPI interrupt */
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
}
|
|
|
|
static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
|
|
armada_xp_mpic_smp_cpu_init();
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
|
|
.notifier_call = armada_xp_mpic_secondary_init,
|
|
.priority = 100,
|
|
};
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
|
|
.map = armada_370_xp_mpic_irq_map,
|
|
.xlate = irq_domain_xlate_onecell,
|
|
};
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
|
|
{
|
|
u32 msimask, msinr;
|
|
|
|
msimask = readl_relaxed(per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
|
|
& PCI_MSI_DOORBELL_MASK;
|
|
|
|
writel(~msimask, per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
for (msinr = PCI_MSI_DOORBELL_START;
|
|
msinr < PCI_MSI_DOORBELL_END; msinr++) {
|
|
int irq;
|
|
|
|
if (!(msimask & BIT(msinr)))
|
|
continue;
|
|
|
|
if (is_chained) {
|
|
irq = irq_find_mapping(armada_370_xp_msi_domain,
|
|
msinr - 16);
|
|
generic_handle_irq(irq);
|
|
} else {
|
|
irq = msinr - 16;
|
|
handle_domain_irq(armada_370_xp_msi_domain,
|
|
irq, regs);
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
|
|
#endif
|
|
|
|
static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
|
|
struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = irq_get_chip(irq);
|
|
unsigned long irqmap, irqn;
|
|
unsigned int cascade_irq;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
|
|
|
|
if (irqmap & BIT(0)) {
|
|
armada_370_xp_handle_msi_irq(NULL, true);
|
|
irqmap &= ~BIT(0);
|
|
}
|
|
|
|
for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
|
|
cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
|
|
generic_handle_irq(cascade_irq);
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static void __exception_irq_entry
|
|
armada_370_xp_handle_irq(struct pt_regs *regs)
|
|
{
|
|
u32 irqstat, irqnr;
|
|
|
|
do {
|
|
irqstat = readl_relaxed(per_cpu_int_base +
|
|
ARMADA_370_XP_CPU_INTACK_OFFS);
|
|
irqnr = irqstat & 0x3FF;
|
|
|
|
if (irqnr > 1022)
|
|
break;
|
|
|
|
if (irqnr > 1) {
|
|
handle_domain_irq(armada_370_xp_mpic_domain,
|
|
irqnr, regs);
|
|
continue;
|
|
}
|
|
|
|
/* MSI handling */
|
|
if (irqnr == 1)
|
|
armada_370_xp_handle_msi_irq(regs, false);
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* IPI Handling */
|
|
if (irqnr == 0) {
|
|
u32 ipimask, ipinr;
|
|
|
|
ipimask = readl_relaxed(per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
|
|
& IPI_DOORBELL_MASK;
|
|
|
|
writel(~ipimask, per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
/* Handle all pending doorbells */
|
|
for (ipinr = IPI_DOORBELL_START;
|
|
ipinr < IPI_DOORBELL_END; ipinr++) {
|
|
if (ipimask & (0x1 << ipinr))
|
|
handle_IPI(ipinr, regs);
|
|
}
|
|
continue;
|
|
}
|
|
#endif
|
|
|
|
} while (1);
|
|
}
|
|
|
|
static int __init armada_370_xp_mpic_of_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
struct resource main_int_res, per_cpu_int_res;
|
|
int parent_irq, nr_irqs, i;
|
|
u32 control;
|
|
|
|
BUG_ON(of_address_to_resource(node, 0, &main_int_res));
|
|
BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
|
|
|
|
BUG_ON(!request_mem_region(main_int_res.start,
|
|
resource_size(&main_int_res),
|
|
node->full_name));
|
|
BUG_ON(!request_mem_region(per_cpu_int_res.start,
|
|
resource_size(&per_cpu_int_res),
|
|
node->full_name));
|
|
|
|
main_int_base = ioremap(main_int_res.start,
|
|
resource_size(&main_int_res));
|
|
BUG_ON(!main_int_base);
|
|
|
|
per_cpu_int_base = ioremap(per_cpu_int_res.start,
|
|
resource_size(&per_cpu_int_res));
|
|
BUG_ON(!per_cpu_int_base);
|
|
|
|
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
|
|
nr_irqs = (control >> 2) & 0x3ff;
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
|
|
|
|
armada_370_xp_mpic_domain =
|
|
irq_domain_add_linear(node, nr_irqs,
|
|
&armada_370_xp_mpic_irq_ops, NULL);
|
|
|
|
BUG_ON(!armada_370_xp_mpic_domain);
|
|
|
|
#ifdef CONFIG_SMP
|
|
armada_xp_mpic_smp_cpu_init();
|
|
#endif
|
|
|
|
armada_370_xp_msi_init(node, main_int_res.start);
|
|
|
|
parent_irq = irq_of_parse_and_map(node, 0);
|
|
if (parent_irq <= 0) {
|
|
irq_set_default_host(armada_370_xp_mpic_domain);
|
|
set_handle_irq(armada_370_xp_handle_irq);
|
|
#ifdef CONFIG_SMP
|
|
set_smp_cross_call(armada_mpic_send_doorbell);
|
|
register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
|
|
#endif
|
|
} else {
|
|
irq_set_chained_handler(parent_irq,
|
|
armada_370_xp_mpic_handle_cascade_irq);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
|