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![Xiubo Li](/assets/img/avatar_default.png)
The regmap core supports different endian modes for devices. This patch convert to direct regmap API usage, preparing to support big endianness for LS1 SoC. Using the regmap framework it will be easy to support devices that only differ in endianness with the same device driver. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
500 lines
11 KiB
C
500 lines
11 KiB
C
/*
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* Freescale FlexTimer Module (FTM) PWM Driver
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*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#define FTM_SC 0x00
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#define FTM_SC_CLK_MASK_SHIFT 3
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#define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT)
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#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
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#define FTM_SC_PS_MASK 0x7
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#define FTM_CNT 0x04
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#define FTM_MOD 0x08
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#define FTM_CSC_BASE 0x0C
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#define FTM_CSC_MSB BIT(5)
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#define FTM_CSC_MSA BIT(4)
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#define FTM_CSC_ELSB BIT(3)
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#define FTM_CSC_ELSA BIT(2)
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#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8))
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#define FTM_CV_BASE 0x10
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#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8))
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#define FTM_CNTIN 0x4C
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#define FTM_STATUS 0x50
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#define FTM_MODE 0x54
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#define FTM_MODE_FTMEN BIT(0)
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#define FTM_MODE_INIT BIT(2)
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#define FTM_MODE_PWMSYNC BIT(3)
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#define FTM_SYNC 0x58
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#define FTM_OUTINIT 0x5C
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#define FTM_OUTMASK 0x60
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#define FTM_COMBINE 0x64
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#define FTM_DEADTIME 0x68
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#define FTM_EXTTRIG 0x6C
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#define FTM_POL 0x70
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#define FTM_FMS 0x74
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#define FTM_FILTER 0x78
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#define FTM_FLTCTRL 0x7C
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#define FTM_QDCTRL 0x80
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#define FTM_CONF 0x84
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#define FTM_FLTPOL 0x88
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#define FTM_SYNCONF 0x8C
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#define FTM_INVCTRL 0x90
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#define FTM_SWOCTRL 0x94
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#define FTM_PWMLOAD 0x98
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enum fsl_pwm_clk {
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FSL_PWM_CLK_SYS,
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FSL_PWM_CLK_FIX,
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FSL_PWM_CLK_EXT,
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FSL_PWM_CLK_CNTEN,
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FSL_PWM_CLK_MAX
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};
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struct fsl_pwm_chip {
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struct pwm_chip chip;
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struct mutex lock;
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unsigned int use_count;
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unsigned int cnt_select;
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unsigned int clk_ps;
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struct regmap *regmap;
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int period_ns;
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struct clk *clk[FSL_PWM_CLK_MAX];
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};
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static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct fsl_pwm_chip, chip);
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}
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static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);
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}
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static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);
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}
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static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc,
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enum fsl_pwm_clk index)
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{
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unsigned long sys_rate, cnt_rate;
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unsigned long long ratio;
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sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]);
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if (!sys_rate)
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return -EINVAL;
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cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]);
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if (!cnt_rate)
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return -EINVAL;
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switch (index) {
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case FSL_PWM_CLK_SYS:
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fpc->clk_ps = 1;
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break;
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case FSL_PWM_CLK_FIX:
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ratio = 2 * cnt_rate - 1;
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do_div(ratio, sys_rate);
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fpc->clk_ps = ratio;
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break;
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case FSL_PWM_CLK_EXT:
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ratio = 4 * cnt_rate - 1;
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do_div(ratio, sys_rate);
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fpc->clk_ps = ratio;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc,
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unsigned long period_ns)
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{
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unsigned long long c, c0;
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c = clk_get_rate(fpc->clk[fpc->cnt_select]);
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c = c * period_ns;
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do_div(c, 1000000000UL);
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do {
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c0 = c;
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do_div(c0, (1 << fpc->clk_ps));
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if (c0 <= 0xFFFF)
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return (unsigned long)c0;
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} while (++fpc->clk_ps < 8);
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return 0;
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}
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static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc,
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unsigned long period_ns,
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enum fsl_pwm_clk index)
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{
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int ret;
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ret = fsl_pwm_calculate_default_ps(fpc, index);
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if (ret) {
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dev_err(fpc->chip.dev,
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"failed to calculate default prescaler: %d\n",
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ret);
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return 0;
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}
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return fsl_pwm_calculate_cycles(fpc, period_ns);
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}
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static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
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unsigned long period_ns)
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{
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enum fsl_pwm_clk m0, m1;
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unsigned long fix_rate, ext_rate, cycles;
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cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns,
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FSL_PWM_CLK_SYS);
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if (cycles) {
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fpc->cnt_select = FSL_PWM_CLK_SYS;
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return cycles;
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}
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fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
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ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
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if (fix_rate > ext_rate) {
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m0 = FSL_PWM_CLK_FIX;
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m1 = FSL_PWM_CLK_EXT;
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} else {
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m0 = FSL_PWM_CLK_EXT;
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m1 = FSL_PWM_CLK_FIX;
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}
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cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0);
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if (cycles) {
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fpc->cnt_select = m0;
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return cycles;
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}
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fpc->cnt_select = m1;
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return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1);
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}
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static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
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unsigned long period_ns,
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unsigned long duty_ns)
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{
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unsigned long long duty;
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u32 val;
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regmap_read(fpc->regmap, FTM_MOD, &val);
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duty = (unsigned long long)duty_ns * (val + 1);
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do_div(duty, period_ns);
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return (unsigned long)duty;
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}
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static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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u32 period, duty;
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mutex_lock(&fpc->lock);
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/*
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* The Freescale FTM controller supports only a single period for
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* all PWM channels, therefore incompatible changes need to be
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* refused.
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*/
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if (fpc->period_ns && fpc->period_ns != period_ns) {
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dev_err(fpc->chip.dev,
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"conflicting period requested for PWM %u\n",
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pwm->hwpwm);
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mutex_unlock(&fpc->lock);
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return -EBUSY;
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}
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if (!fpc->period_ns && duty_ns) {
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period = fsl_pwm_calculate_period(fpc, period_ns);
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if (!period) {
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dev_err(fpc->chip.dev, "failed to calculate period\n");
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mutex_unlock(&fpc->lock);
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return -EINVAL;
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}
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regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
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fpc->clk_ps);
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regmap_write(fpc->regmap, FTM_MOD, period - 1);
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fpc->period_ns = period_ns;
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}
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mutex_unlock(&fpc->lock);
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duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns);
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regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
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FTM_CSC_MSB | FTM_CSC_ELSB);
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regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
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return 0;
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}
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static int fsl_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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u32 val;
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regmap_read(fpc->regmap, FTM_POL, &val);
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if (polarity == PWM_POLARITY_INVERSED)
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val |= BIT(pwm->hwpwm);
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else
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val &= ~BIT(pwm->hwpwm);
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regmap_write(fpc->regmap, FTM_POL, val);
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return 0;
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}
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static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
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{
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int ret;
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if (fpc->use_count != 0)
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return 0;
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/* select counter clock source */
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regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
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FTM_SC_CLK(fpc->cnt_select));
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ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);
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if (ret)
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return ret;
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ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
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if (ret) {
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clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
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return ret;
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}
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fpc->use_count++;
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return 0;
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}
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static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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int ret;
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mutex_lock(&fpc->lock);
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regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0);
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ret = fsl_counter_clock_enable(fpc);
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mutex_unlock(&fpc->lock);
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return ret;
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}
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static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc)
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{
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/*
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* already disabled, do nothing
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*/
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if (fpc->use_count == 0)
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return;
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/* there are still users, so can't disable yet */
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if (--fpc->use_count > 0)
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return;
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/* no users left, disable PWM counter clock */
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regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 0);
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clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
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clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
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}
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static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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u32 val;
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mutex_lock(&fpc->lock);
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regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
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BIT(pwm->hwpwm));
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fsl_counter_clock_disable(fpc);
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regmap_read(fpc->regmap, FTM_OUTMASK, &val);
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if ((val & 0xFF) == 0xFF)
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fpc->period_ns = 0;
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mutex_unlock(&fpc->lock);
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}
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static const struct pwm_ops fsl_pwm_ops = {
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.request = fsl_pwm_request,
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.free = fsl_pwm_free,
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.config = fsl_pwm_config,
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.set_polarity = fsl_pwm_set_polarity,
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.enable = fsl_pwm_enable,
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.disable = fsl_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
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{
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int ret;
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ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);
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if (ret)
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return ret;
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regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
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regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
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regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
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clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);
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return 0;
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}
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static const struct regmap_config fsl_pwm_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = FTM_PWMLOAD,
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};
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static int fsl_pwm_probe(struct platform_device *pdev)
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{
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struct fsl_pwm_chip *fpc;
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struct resource *res;
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void __iomem *base;
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int ret;
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fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
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if (!fpc)
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return -ENOMEM;
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mutex_init(&fpc->lock);
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fpc->chip.dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
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&fsl_pwm_regmap_config);
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if (IS_ERR(fpc->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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return PTR_ERR(fpc->regmap);
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}
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fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
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if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
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dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
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return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
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}
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fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
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if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
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return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
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fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
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if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
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return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
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fpc->clk[FSL_PWM_CLK_CNTEN] =
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devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
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if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
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return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
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fpc->chip.ops = &fsl_pwm_ops;
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fpc->chip.of_xlate = of_pwm_xlate_with_flags;
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fpc->chip.of_pwm_n_cells = 3;
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fpc->chip.base = -1;
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fpc->chip.npwm = 8;
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fpc->chip.can_sleep = true;
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ret = pwmchip_add(&fpc->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, fpc);
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return fsl_pwm_init(fpc);
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}
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static int fsl_pwm_remove(struct platform_device *pdev)
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{
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struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);
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return pwmchip_remove(&fpc->chip);
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}
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static const struct of_device_id fsl_pwm_dt_ids[] = {
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{ .compatible = "fsl,vf610-ftm-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
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static struct platform_driver fsl_pwm_driver = {
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.driver = {
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.name = "fsl-ftm-pwm",
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.of_match_table = fsl_pwm_dt_ids,
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|
},
|
|
.probe = fsl_pwm_probe,
|
|
.remove = fsl_pwm_remove,
|
|
};
|
|
module_platform_driver(fsl_pwm_driver);
|
|
|
|
MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
|
|
MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
|
|
MODULE_ALIAS("platform:fsl-ftm-pwm");
|
|
MODULE_LICENSE("GPL");
|