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![Xiubo Li](/assets/img/avatar_default.png)
Sort all the include headers alphabetically for the freescale spi drivers. If the inlcude headers sorted out of order, maybe the best logical choice is to append new ones after the exist ones, while this may create a lot of potential for duplicates and conflicts for each diffenent changes will add new headers in the same location. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
232 lines
5.8 KiB
C
232 lines
5.8 KiB
C
/*
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* Freescale SPI/eSPI controller driver library.
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*
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* Maintainer: Kumar Gala
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*
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* Copyright (C) 2006 Polycom, Inc.
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*
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* CPM SPI and QE buffer descriptors mode support:
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/fsl_devices.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/of_platform.h>
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#include <linux/spi/spi.h>
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#ifdef CONFIG_FSL_SOC
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#include <sysdev/fsl_soc.h>
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#endif
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#include "spi-fsl-lib.h"
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#define MPC8XXX_SPI_RX_BUF(type) \
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void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
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{ \
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type *rx = mpc8xxx_spi->rx; \
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*rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
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mpc8xxx_spi->rx = rx; \
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}
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#define MPC8XXX_SPI_TX_BUF(type) \
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u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
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{ \
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u32 data; \
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const type *tx = mpc8xxx_spi->tx; \
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if (!tx) \
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return 0; \
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data = *tx++ << mpc8xxx_spi->tx_shift; \
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mpc8xxx_spi->tx = tx; \
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return data; \
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}
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MPC8XXX_SPI_RX_BUF(u8)
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MPC8XXX_SPI_RX_BUF(u16)
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MPC8XXX_SPI_RX_BUF(u32)
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MPC8XXX_SPI_TX_BUF(u8)
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MPC8XXX_SPI_TX_BUF(u16)
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MPC8XXX_SPI_TX_BUF(u32)
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struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
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{
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return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
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}
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static void mpc8xxx_spi_work(struct work_struct *work)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
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work);
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spin_lock_irq(&mpc8xxx_spi->lock);
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while (!list_empty(&mpc8xxx_spi->queue)) {
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struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
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struct spi_message, queue);
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list_del_init(&m->queue);
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spin_unlock_irq(&mpc8xxx_spi->lock);
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if (mpc8xxx_spi->spi_do_one_msg)
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mpc8xxx_spi->spi_do_one_msg(m);
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spin_lock_irq(&mpc8xxx_spi->lock);
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}
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spin_unlock_irq(&mpc8xxx_spi->lock);
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}
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int mpc8xxx_spi_transfer(struct spi_device *spi,
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struct spi_message *m)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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unsigned long flags;
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m->actual_length = 0;
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m->status = -EINPROGRESS;
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spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
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list_add_tail(&m->queue, &mpc8xxx_spi->queue);
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queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
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spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
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return 0;
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}
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const char *mpc8xxx_spi_strmode(unsigned int flags)
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{
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if (flags & SPI_QE_CPU_MODE) {
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return "QE CPU";
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} else if (flags & SPI_CPM_MODE) {
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if (flags & SPI_QE)
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return "QE";
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else if (flags & SPI_CPM2)
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return "CPM2";
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else
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return "CPM1";
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}
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return "CPU";
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}
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int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
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unsigned int irq)
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{
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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struct spi_master *master;
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struct mpc8xxx_spi *mpc8xxx_spi;
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int ret = 0;
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master = dev_get_drvdata(dev);
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/* the spi->mode bits understood by this driver: */
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
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| SPI_LSB_FIRST | SPI_LOOP;
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master->transfer = mpc8xxx_spi_transfer;
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master->dev.of_node = dev->of_node;
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mpc8xxx_spi = spi_master_get_devdata(master);
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mpc8xxx_spi->dev = dev;
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mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
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mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
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mpc8xxx_spi->flags = pdata->flags;
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mpc8xxx_spi->spibrg = pdata->sysclk;
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mpc8xxx_spi->irq = irq;
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mpc8xxx_spi->rx_shift = 0;
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mpc8xxx_spi->tx_shift = 0;
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init_completion(&mpc8xxx_spi->done);
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->max_chipselect;
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spin_lock_init(&mpc8xxx_spi->lock);
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init_completion(&mpc8xxx_spi->done);
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INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
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INIT_LIST_HEAD(&mpc8xxx_spi->queue);
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mpc8xxx_spi->workqueue = create_singlethread_workqueue(
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dev_name(master->dev.parent));
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if (mpc8xxx_spi->workqueue == NULL) {
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ret = -EBUSY;
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goto err;
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}
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return 0;
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err:
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return ret;
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}
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int mpc8xxx_spi_remove(struct device *dev)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct spi_master *master;
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master = dev_get_drvdata(dev);
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mpc8xxx_spi = spi_master_get_devdata(master);
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flush_workqueue(mpc8xxx_spi->workqueue);
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destroy_workqueue(mpc8xxx_spi->workqueue);
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spi_unregister_master(master);
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free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
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if (mpc8xxx_spi->spi_remove)
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mpc8xxx_spi->spi_remove(mpc8xxx_spi);
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return 0;
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}
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int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
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{
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struct device *dev = &ofdev->dev;
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struct device_node *np = ofdev->dev.of_node;
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struct mpc8xxx_spi_probe_info *pinfo;
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struct fsl_spi_platform_data *pdata;
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const void *prop;
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int ret = -ENOMEM;
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pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
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if (!pinfo)
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return ret;
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pdata = &pinfo->pdata;
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dev->platform_data = pdata;
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/* Allocate bus num dynamically. */
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pdata->bus_num = -1;
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#ifdef CONFIG_FSL_SOC
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/* SPI controller is either clocked from QE or SoC clock. */
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pdata->sysclk = get_brgfreq();
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if (pdata->sysclk == -1) {
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pdata->sysclk = fsl_get_sys_freq();
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if (pdata->sysclk == -1)
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return -ENODEV;
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}
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#else
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ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
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if (ret)
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return ret;
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#endif
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prop = of_get_property(np, "mode", NULL);
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if (prop && !strcmp(prop, "cpu-qe"))
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pdata->flags = SPI_QE_CPU_MODE;
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else if (prop && !strcmp(prop, "qe"))
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pdata->flags = SPI_CPM_MODE | SPI_QE;
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else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
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pdata->flags = SPI_CPM_MODE | SPI_CPM2;
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else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
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pdata->flags = SPI_CPM_MODE | SPI_CPM1;
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return 0;
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}
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