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These plls are found in the Tensor gs101 SoC found in the Pixel 6. pll0516x: Integer PLL with high frequency pll0517x: Integer PLL with middle frequency pll0518x: Integer PLL with low frequency PLL0516x FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) PLL0517x and PLL0518x FOUT = (MDIV * FIN)/PDIV*2^SDIV) The PLLs are similar enough to pll_0822x that the same code can handle both. The main difference is the change in the fout formula for the high frequency 0516 pll. Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor. MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x. When defining the PLL the "con" parameter should be set to CON3 register, like this PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-8-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
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Linux kernel ============ There are several guides for kernel developers and users. These guides can be rendered in a number of formats, like HTML and PDF. Please read Documentation/admin-guide/README.rst first. In order to build the documentation, use ``make htmldocs`` or ``make pdfdocs``. The formatted documentation can also be read online at: https://www.kernel.org/doc/html/latest/ There are various text files in the Documentation/ subdirectory, several of them using the Restructured Text markup notation. Please read the Documentation/process/changes.rst file, as it contains the requirements for building and running the kernel, and information about the problems which may result by upgrading your kernel.