linux-stable/arch/x86/kernel/cpu
James Morse 141739aa73 x86/resctrl: Make ctrlval arrays the same size
The CODE and DATA resources report a num_closid that is half the actual
size supported by the hardware. This behaviour is visible to user-space
when CDP is enabled.

The CODE and DATA resources have their own ctrlval arrays which are
half the size of the underlying hardware because num_closid was already
adjusted. One holds the odd configurations values, the other even.

Before the CDP resources can be merged, the 'half the closids' behaviour
needs to be implemented by schemata_list_create(), but this causes the
ctrl_val[] array to be full sized.

Remove the logic from the architecture specific rdt_get_cdp_config()
setup, and add it to schemata_list_create(). Functions that walk all the
configurations, such as domain_setup_ctrlval() and reset_all_ctrls(),
take num_closid directly from struct rdt_hw_resource also have
to halve num_closid as only the lower half of each array is in
use. domain_setup_ctrlval() and reset_all_ctrls() both copy struct
rdt_hw_resource's num_closid to a struct msr_param. Correct the value
here.

This is temporary as a subsequent patch will merge all three ctrl_val[]
arrays such that when CDP is in use, the CODA/DATA layout in the array
matches the hardware. reset_all_ctrls()'s loop over the whole of
ctrl_val[] is not touched as this is harmless, and will be required as
it is once the resources are merged.

Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Jamie Iles <jamie@nuviainc.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Link: https://lkml.kernel.org/r/20210728170637.25610-19-james.morse@arm.com
2021-08-11 17:58:33 +02:00
..
mce Merge branch 'akpm' (patches from Andrew) 2021-06-29 17:29:11 -07:00
microcode x86/microcode: Check for offline CPUs before requesting new microcode 2021-03-22 22:29:40 +01:00
mtrr x86/msr: Rename MSR_K8_SYSCFG to MSR_AMD64_SYSCFG 2021-05-10 07:51:38 +02:00
resctrl x86/resctrl: Make ctrlval arrays the same size 2021-08-11 17:58:33 +02:00
sgx Merge branch 'akpm' (patches from Andrew) 2021-06-29 17:29:11 -07:00
.gitignore .gitignore: add SPDX License Identifier 2020-03-25 11:50:48 +01:00
acrn.c x86/acrn: Introduce acrn_cpuid_base() and hypervisor feature bits 2021-02-09 10:58:18 +01:00
amd.c - New AMD models support 2021-06-28 11:22:40 -07:00
aperfmperf.c x86/cpu: Avoid cpuinfo-induced IPIing of idle CPUs 2020-11-06 16:59:11 -08:00
bugs.c x86/speculation: Fix prctl() when spectre_v2_user={seccomp,prctl},ibpb 2020-11-25 20:17:09 +01:00
cacheinfo.c x86/cacheinfo: Remove unneeded dead-store initialization 2021-04-07 21:12:12 +02:00
centaur.c x86/cpu/centaur: Add Centaur family >=7 CPUs initialization support 2020-09-11 10:53:19 +02:00
common.c Fixes and improvements for FPU handling on x86: 2021-07-07 11:12:01 -07:00
cpu.h x86/tsx: Clear CPUID bits when TSX always force aborts 2021-06-15 17:46:48 +02:00
cpuid-deps.c x86/cpufeatures: Add SGX1 and SGX2 sub-features 2021-03-25 17:33:11 +01:00
cyrix.c x86: Fix various typos in comments 2021-03-18 15:31:53 +01:00
feat_ctl.c x86/cpu/intel: Allow SGX virtualization without Launch Control support 2021-04-06 09:43:41 +02:00
hygon.c perf/x86/rapl: Use CPUID bit on AMD and Hygon parts 2021-06-01 21:10:33 +02:00
hypervisor.c
intel.c Changes in this cycle were: 2021-06-28 13:30:02 -07:00
intel_epb.c
intel_pconfig.c
Makefile x86/sgx: Initialize metadata for Enclave Page Cache (EPC) sections 2020-11-17 14:36:13 +01:00
match.c x86/cpu: Add a steppings field to struct x86_cpu_id 2020-04-20 12:19:21 +02:00
mkcapflags.sh x86/cpu: Print VMX flags in /proc/cpuinfo using VMX_FEATURES_* 2020-01-13 18:36:02 +01:00
mshyperv.c Revert "x86/hyperv: fix logical processor creation" 2021-07-21 15:55:43 +00:00
perfctr-watchdog.c x86/nmi_watchdog: Fix old-style NMI watchdog regression on old Intel CPUs 2021-06-10 10:04:40 +02:00
powerflags.c
proc.c x86/cpu: Print VMX flags in /proc/cpuinfo using VMX_FEATURES_* 2020-01-13 18:36:02 +01:00
rdrand.c x86/rdrand: Sanity-check RDRAND output 2019-10-01 19:55:32 +02:00
scattered.c x86/cpufeatures: Add SGX1 and SGX2 sub-features 2021-03-25 17:33:11 +01:00
topology.c x86: Fix various typos in comments 2021-03-18 15:31:53 +01:00
transmeta.c
tsx.c x86/tsx: Clear CPUID bits when TSX always force aborts 2021-06-15 17:46:48 +02:00
umc.c
umwait.c KVM: VMX: Stop context switching MSR_IA32_UMWAIT_CONTROL 2020-06-22 20:54:57 -04:00
vmware.c Have vmware guests skip the refined TSC calibration when the TSC 2021-04-26 09:13:43 -07:00
zhaoxin.c x86/cpu: Reinitialize IA32_FEAT_CTL MSR on BSP during wakeup 2020-06-15 14:18:37 +02:00