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![Bjorn Helgaas](/assets/img/avatar_default.png)
pcie_cap_has_devctl() does nothing, so remove it. Simplicity over consistency in this case. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-By: Jiang Liu <jiang.liu@huawei.com>
669 lines
16 KiB
C
669 lines
16 KiB
C
#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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#include <linux/wait.h>
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#include "pci.h"
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/*
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* This interrupt-safe spinlock protects all accesses to PCI
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* configuration space.
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*/
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DEFINE_RAW_SPINLOCK(pci_lock);
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/*
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* Wrappers for all PCI configuration access functions. They just check
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* alignment, do locking and call the low-level functions pointed to
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* by pci_dev->ops.
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*/
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#define PCI_byte_BAD 0
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#define PCI_word_BAD (pos & 1)
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#define PCI_dword_BAD (pos & 3)
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#define PCI_OP_READ(size,type,len) \
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int pci_bus_read_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
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{ \
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int res; \
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unsigned long flags; \
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u32 data = 0; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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raw_spin_lock_irqsave(&pci_lock, flags); \
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res = bus->ops->read(bus, devfn, pos, len, &data); \
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*value = (type)data; \
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raw_spin_unlock_irqrestore(&pci_lock, flags); \
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return res; \
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}
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#define PCI_OP_WRITE(size,type,len) \
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int pci_bus_write_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
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{ \
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int res; \
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unsigned long flags; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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raw_spin_lock_irqsave(&pci_lock, flags); \
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res = bus->ops->write(bus, devfn, pos, len, value); \
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raw_spin_unlock_irqrestore(&pci_lock, flags); \
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return res; \
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}
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PCI_OP_READ(byte, u8, 1)
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PCI_OP_READ(word, u16, 2)
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PCI_OP_READ(dword, u32, 4)
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PCI_OP_WRITE(byte, u8, 1)
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PCI_OP_WRITE(word, u16, 2)
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PCI_OP_WRITE(dword, u32, 4)
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EXPORT_SYMBOL(pci_bus_read_config_byte);
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EXPORT_SYMBOL(pci_bus_read_config_word);
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EXPORT_SYMBOL(pci_bus_read_config_dword);
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EXPORT_SYMBOL(pci_bus_write_config_byte);
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EXPORT_SYMBOL(pci_bus_write_config_word);
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EXPORT_SYMBOL(pci_bus_write_config_dword);
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/**
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* pci_bus_set_ops - Set raw operations of pci bus
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* @bus: pci bus struct
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* @ops: new raw operations
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*
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* Return previous raw operations
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*/
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struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
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{
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struct pci_ops *old_ops;
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_lock, flags);
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old_ops = bus->ops;
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bus->ops = ops;
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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return old_ops;
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}
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EXPORT_SYMBOL(pci_bus_set_ops);
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/**
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* pci_read_vpd - Read one entry from Vital Product Data
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* @dev: pci device struct
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* @pos: offset in vpd space
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* @count: number of bytes to read
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* @buf: pointer to where to store result
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*
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*/
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ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
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{
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if (!dev->vpd || !dev->vpd->ops)
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return -ENODEV;
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return dev->vpd->ops->read(dev, pos, count, buf);
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}
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EXPORT_SYMBOL(pci_read_vpd);
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/**
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* pci_write_vpd - Write entry to Vital Product Data
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* @dev: pci device struct
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* @pos: offset in vpd space
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* @count: number of bytes to write
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* @buf: buffer containing write data
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*
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*/
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ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
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{
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if (!dev->vpd || !dev->vpd->ops)
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return -ENODEV;
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return dev->vpd->ops->write(dev, pos, count, buf);
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}
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EXPORT_SYMBOL(pci_write_vpd);
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/*
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* The following routines are to prevent the user from accessing PCI config
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* space when it's unsafe to do so. Some devices require this during BIST and
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* we're required to prevent it during D-state transitions.
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*
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* We have a bit per device to indicate it's blocked and a global wait queue
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* for callers to sleep on until devices are unblocked.
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*/
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static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
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static noinline void pci_wait_cfg(struct pci_dev *dev)
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{
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DECLARE_WAITQUEUE(wait, current);
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__add_wait_queue(&pci_cfg_wait, &wait);
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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raw_spin_unlock_irq(&pci_lock);
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schedule();
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raw_spin_lock_irq(&pci_lock);
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} while (dev->block_cfg_access);
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__remove_wait_queue(&pci_cfg_wait, &wait);
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}
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/* Returns 0 on success, negative values indicate error. */
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#define PCI_USER_READ_CONFIG(size,type) \
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int pci_user_read_config_##size \
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(struct pci_dev *dev, int pos, type *val) \
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{ \
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int ret = 0; \
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u32 data = -1; \
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if (PCI_##size##_BAD) \
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return -EINVAL; \
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raw_spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_cfg_access)) \
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pci_wait_cfg(dev); \
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ret = dev->bus->ops->read(dev->bus, dev->devfn, \
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pos, sizeof(type), &data); \
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raw_spin_unlock_irq(&pci_lock); \
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*val = (type)data; \
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if (ret > 0) \
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ret = -EINVAL; \
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return ret; \
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} \
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EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
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/* Returns 0 on success, negative values indicate error. */
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#define PCI_USER_WRITE_CONFIG(size,type) \
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int pci_user_write_config_##size \
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(struct pci_dev *dev, int pos, type val) \
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{ \
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int ret = -EIO; \
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if (PCI_##size##_BAD) \
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return -EINVAL; \
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raw_spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_cfg_access)) \
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pci_wait_cfg(dev); \
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ret = dev->bus->ops->write(dev->bus, dev->devfn, \
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pos, sizeof(type), val); \
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raw_spin_unlock_irq(&pci_lock); \
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if (ret > 0) \
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ret = -EINVAL; \
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return ret; \
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} \
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EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
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PCI_USER_READ_CONFIG(byte, u8)
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PCI_USER_READ_CONFIG(word, u16)
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PCI_USER_READ_CONFIG(dword, u32)
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PCI_USER_WRITE_CONFIG(byte, u8)
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PCI_USER_WRITE_CONFIG(word, u16)
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PCI_USER_WRITE_CONFIG(dword, u32)
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/* VPD access through PCI 2.2+ VPD capability */
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#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
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struct pci_vpd_pci22 {
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struct pci_vpd base;
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struct mutex lock;
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u16 flag;
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bool busy;
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u8 cap;
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};
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/*
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* Wait for last operation to complete.
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* This code has to spin since there is no other notification from the PCI
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* hardware. Since the VPD is often implemented by serial attachment to an
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* EEPROM, it may take many milliseconds to complete.
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*
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* Returns 0 on success, negative values indicate error.
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*/
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static int pci_vpd_pci22_wait(struct pci_dev *dev)
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{
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struct pci_vpd_pci22 *vpd =
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container_of(dev->vpd, struct pci_vpd_pci22, base);
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unsigned long timeout = jiffies + HZ/20 + 2;
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u16 status;
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int ret;
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if (!vpd->busy)
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return 0;
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for (;;) {
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ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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&status);
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if (ret < 0)
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return ret;
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if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
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vpd->busy = false;
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return 0;
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}
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if (time_after(jiffies, timeout)) {
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dev_printk(KERN_DEBUG, &dev->dev,
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"vpd r/w failed. This is likely a firmware "
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"bug on this device. Contact the card "
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"vendor for a firmware update.");
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return -ETIMEDOUT;
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}
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if (fatal_signal_pending(current))
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return -EINTR;
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if (!cond_resched())
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udelay(10);
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}
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}
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static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
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void *arg)
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{
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struct pci_vpd_pci22 *vpd =
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container_of(dev->vpd, struct pci_vpd_pci22, base);
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int ret;
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loff_t end = pos + count;
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u8 *buf = arg;
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if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
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return -EINVAL;
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if (mutex_lock_killable(&vpd->lock))
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return -EINTR;
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ret = pci_vpd_pci22_wait(dev);
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if (ret < 0)
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goto out;
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while (pos < end) {
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u32 val;
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unsigned int i, skip;
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ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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pos & ~3);
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if (ret < 0)
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break;
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vpd->busy = true;
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vpd->flag = PCI_VPD_ADDR_F;
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ret = pci_vpd_pci22_wait(dev);
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if (ret < 0)
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break;
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ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
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if (ret < 0)
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break;
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skip = pos & 3;
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for (i = 0; i < sizeof(u32); i++) {
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if (i >= skip) {
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*buf++ = val;
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if (++pos == end)
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break;
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}
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val >>= 8;
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}
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}
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out:
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mutex_unlock(&vpd->lock);
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return ret ? ret : count;
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}
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static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
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const void *arg)
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{
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struct pci_vpd_pci22 *vpd =
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container_of(dev->vpd, struct pci_vpd_pci22, base);
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const u8 *buf = arg;
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loff_t end = pos + count;
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int ret = 0;
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if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
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return -EINVAL;
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if (mutex_lock_killable(&vpd->lock))
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return -EINTR;
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ret = pci_vpd_pci22_wait(dev);
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if (ret < 0)
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goto out;
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while (pos < end) {
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u32 val;
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val = *buf++;
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val |= *buf++ << 8;
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val |= *buf++ << 16;
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val |= *buf++ << 24;
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ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
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if (ret < 0)
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break;
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ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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pos | PCI_VPD_ADDR_F);
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if (ret < 0)
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break;
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vpd->busy = true;
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vpd->flag = 0;
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ret = pci_vpd_pci22_wait(dev);
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if (ret < 0)
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break;
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pos += sizeof(u32);
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}
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out:
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mutex_unlock(&vpd->lock);
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return ret ? ret : count;
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}
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static void pci_vpd_pci22_release(struct pci_dev *dev)
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{
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kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
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}
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static const struct pci_vpd_ops pci_vpd_pci22_ops = {
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.read = pci_vpd_pci22_read,
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.write = pci_vpd_pci22_write,
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.release = pci_vpd_pci22_release,
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};
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int pci_vpd_pci22_init(struct pci_dev *dev)
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{
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struct pci_vpd_pci22 *vpd;
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u8 cap;
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cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
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if (!cap)
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return -ENODEV;
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vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
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if (!vpd)
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return -ENOMEM;
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vpd->base.len = PCI_VPD_PCI22_SIZE;
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vpd->base.ops = &pci_vpd_pci22_ops;
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mutex_init(&vpd->lock);
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vpd->cap = cap;
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vpd->busy = false;
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dev->vpd = &vpd->base;
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return 0;
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}
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/**
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* pci_vpd_truncate - Set available Vital Product Data size
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* @dev: pci device struct
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* @size: available memory in bytes
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*
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* Adjust size of available VPD area.
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*/
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int pci_vpd_truncate(struct pci_dev *dev, size_t size)
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{
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if (!dev->vpd)
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return -EINVAL;
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/* limited by the access method */
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if (size > dev->vpd->len)
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return -EINVAL;
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dev->vpd->len = size;
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if (dev->vpd->attr)
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dev->vpd->attr->size = size;
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return 0;
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}
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EXPORT_SYMBOL(pci_vpd_truncate);
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/**
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* pci_cfg_access_lock - Lock PCI config reads/writes
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* @dev: pci device struct
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*
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* When access is locked, any userspace reads or writes to config
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* space and concurrent lock requests will sleep until access is
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* allowed via pci_cfg_access_unlocked again.
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*/
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void pci_cfg_access_lock(struct pci_dev *dev)
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{
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might_sleep();
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raw_spin_lock_irq(&pci_lock);
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if (dev->block_cfg_access)
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pci_wait_cfg(dev);
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dev->block_cfg_access = 1;
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raw_spin_unlock_irq(&pci_lock);
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}
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EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
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/**
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* pci_cfg_access_trylock - try to lock PCI config reads/writes
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* @dev: pci device struct
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*
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* Same as pci_cfg_access_lock, but will return 0 if access is
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* already locked, 1 otherwise. This function can be used from
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* atomic contexts.
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*/
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bool pci_cfg_access_trylock(struct pci_dev *dev)
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{
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unsigned long flags;
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bool locked = true;
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raw_spin_lock_irqsave(&pci_lock, flags);
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if (dev->block_cfg_access)
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locked = false;
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else
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dev->block_cfg_access = 1;
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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return locked;
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}
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EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
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/**
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* pci_cfg_access_unlock - Unlock PCI config reads/writes
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* @dev: pci device struct
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*
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* This function allows PCI config accesses to resume.
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*/
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void pci_cfg_access_unlock(struct pci_dev *dev)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_lock, flags);
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/* This indicates a problem in the caller, but we don't need
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* to kill them, unlike a double-block above. */
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WARN_ON(!dev->block_cfg_access);
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dev->block_cfg_access = 0;
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wake_up_all(&pci_cfg_wait);
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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}
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EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
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static inline int pcie_cap_version(const struct pci_dev *dev)
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{
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return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
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}
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static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return type == PCI_EXP_TYPE_ENDPOINT ||
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type == PCI_EXP_TYPE_LEG_END ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_UPSTREAM ||
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type == PCI_EXP_TYPE_DOWNSTREAM ||
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type == PCI_EXP_TYPE_PCI_BRIDGE ||
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type == PCI_EXP_TYPE_PCIE_BRIDGE;
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}
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static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return (type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_DOWNSTREAM) &&
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pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
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}
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static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
type == PCI_EXP_TYPE_RC_EC;
|
|
}
|
|
|
|
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
|
|
{
|
|
if (!pci_is_pcie(dev))
|
|
return false;
|
|
|
|
switch (pos) {
|
|
case PCI_EXP_FLAGS:
|
|
return true;
|
|
case PCI_EXP_DEVCAP:
|
|
case PCI_EXP_DEVCTL:
|
|
case PCI_EXP_DEVSTA:
|
|
return true;
|
|
case PCI_EXP_LNKCAP:
|
|
case PCI_EXP_LNKCTL:
|
|
case PCI_EXP_LNKSTA:
|
|
return pcie_cap_has_lnkctl(dev);
|
|
case PCI_EXP_SLTCAP:
|
|
case PCI_EXP_SLTCTL:
|
|
case PCI_EXP_SLTSTA:
|
|
return pcie_cap_has_sltctl(dev);
|
|
case PCI_EXP_RTCTL:
|
|
case PCI_EXP_RTCAP:
|
|
case PCI_EXP_RTSTA:
|
|
return pcie_cap_has_rtctl(dev);
|
|
case PCI_EXP_DEVCAP2:
|
|
case PCI_EXP_DEVCTL2:
|
|
case PCI_EXP_LNKCAP2:
|
|
case PCI_EXP_LNKCTL2:
|
|
case PCI_EXP_LNKSTA2:
|
|
return pcie_cap_version(dev) > 1;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Note that these accessor functions are only for the "PCI Express
|
|
* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
|
|
* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
|
|
*/
|
|
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
|
|
{
|
|
int ret;
|
|
|
|
*val = 0;
|
|
if (pos & 1)
|
|
return -EINVAL;
|
|
|
|
if (pcie_capability_reg_implemented(dev, pos)) {
|
|
ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
|
/*
|
|
* Reset *val to 0 if pci_read_config_word() fails, it may
|
|
* have been written as 0xFFFF if hardware error happens
|
|
* during pci_read_config_word().
|
|
*/
|
|
if (ret)
|
|
*val = 0;
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* For Functions that do not implement the Slot Capabilities,
|
|
* Slot Status, and Slot Control registers, these spaces must
|
|
* be hardwired to 0b, with the exception of the Presence Detect
|
|
* State bit in the Slot Status register of Downstream Ports,
|
|
* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
|
|
*/
|
|
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
|
|
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
|
*val = PCI_EXP_SLTSTA_PDS;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_read_word);
|
|
|
|
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
|
|
{
|
|
int ret;
|
|
|
|
*val = 0;
|
|
if (pos & 3)
|
|
return -EINVAL;
|
|
|
|
if (pcie_capability_reg_implemented(dev, pos)) {
|
|
ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
/*
|
|
* Reset *val to 0 if pci_read_config_dword() fails, it may
|
|
* have been written as 0xFFFFFFFF if hardware error happens
|
|
* during pci_read_config_dword().
|
|
*/
|
|
if (ret)
|
|
*val = 0;
|
|
return ret;
|
|
}
|
|
|
|
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
|
|
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
|
*val = PCI_EXP_SLTSTA_PDS;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_read_dword);
|
|
|
|
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
|
|
{
|
|
if (pos & 1)
|
|
return -EINVAL;
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
return 0;
|
|
|
|
return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_write_word);
|
|
|
|
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
|
|
{
|
|
if (pos & 3)
|
|
return -EINVAL;
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
return 0;
|
|
|
|
return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_write_dword);
|
|
|
|
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
|
|
u16 clear, u16 set)
|
|
{
|
|
int ret;
|
|
u16 val;
|
|
|
|
ret = pcie_capability_read_word(dev, pos, &val);
|
|
if (!ret) {
|
|
val &= ~clear;
|
|
val |= set;
|
|
ret = pcie_capability_write_word(dev, pos, val);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
|
|
|
|
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
|
|
u32 clear, u32 set)
|
|
{
|
|
int ret;
|
|
u32 val;
|
|
|
|
ret = pcie_capability_read_dword(dev, pos, &val);
|
|
if (!ret) {
|
|
val &= ~clear;
|
|
val |= set;
|
|
ret = pcie_capability_write_dword(dev, pos, val);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
|