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869f30782c
To properly support a line of Huawei laptops with an AMD CPU and an ES8336 codec connected to the ACP3X module, we need to enable the codec option to divide the MCLK by 2. This is needed because for at least one SKU that has a 48Mhz MCLK the sound is distorted unless the MCLK div by 2 option is enabled. The option to divide the MCLK will first be tried. If no suitable clocking can be generated from this frequency, then the normal non-halved MCLK frequency will be tried. Signed-off-by: Marian Postevca <posteuca@mutex.one> Link: https://lore.kernel.org/r/20230829220116.1159-4-posteuca@mutex.one Signed-off-by: Mark Brown <broonie@kernel.org>
135 lines
3.2 KiB
C
135 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright Everest Semiconductor Co.,Ltd
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*
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* Author: David Yang <yangxiaohua@everest-semi.com>
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*/
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#ifndef _ES8316_H
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#define _ES8316_H
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/*
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* ES8316 register space
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*/
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/* Reset Control */
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#define ES8316_RESET 0x00
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/* Clock Management */
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#define ES8316_CLKMGR_CLKSW 0x01
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#define ES8316_CLKMGR_CLKSEL 0x02
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#define ES8316_CLKMGR_ADCOSR 0x03
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#define ES8316_CLKMGR_ADCDIV1 0x04
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#define ES8316_CLKMGR_ADCDIV2 0x05
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#define ES8316_CLKMGR_DACDIV1 0x06
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#define ES8316_CLKMGR_DACDIV2 0x07
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#define ES8316_CLKMGR_CPDIV 0x08
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/* Serial Data Port Control */
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#define ES8316_SERDATA1 0x09
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#define ES8316_SERDATA_ADC 0x0a
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#define ES8316_SERDATA_DAC 0x0b
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/* System Control */
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#define ES8316_SYS_VMIDSEL 0x0c
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#define ES8316_SYS_PDN 0x0d
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#define ES8316_SYS_LP1 0x0e
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#define ES8316_SYS_LP2 0x0f
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#define ES8316_SYS_VMIDLOW 0x10
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#define ES8316_SYS_VSEL 0x11
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#define ES8316_SYS_REF 0x12
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/* Headphone Mixer */
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#define ES8316_HPMIX_SEL 0x13
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#define ES8316_HPMIX_SWITCH 0x14
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#define ES8316_HPMIX_PDN 0x15
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#define ES8316_HPMIX_VOL 0x16
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/* Charge Pump Headphone driver */
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#define ES8316_CPHP_OUTEN 0x17
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#define ES8316_CPHP_ICAL_VOL 0x18
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#define ES8316_CPHP_PDN1 0x19
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#define ES8316_CPHP_PDN2 0x1a
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#define ES8316_CPHP_LDOCTL 0x1b
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/* Calibration */
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#define ES8316_CAL_TYPE 0x1c
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#define ES8316_CAL_SET 0x1d
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#define ES8316_CAL_HPLIV 0x1e
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#define ES8316_CAL_HPRIV 0x1f
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#define ES8316_CAL_HPLMV 0x20
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#define ES8316_CAL_HPRMV 0x21
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/* ADC Control */
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#define ES8316_ADC_PDN_LINSEL 0x22
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#define ES8316_ADC_PGAGAIN 0x23
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#define ES8316_ADC_D2SEPGA 0x24
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#define ES8316_ADC_DMIC 0x25
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#define ES8316_ADC_MUTE 0x26
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#define ES8316_ADC_VOLUME 0x27
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#define ES8316_ADC_ALC1 0x29
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#define ES8316_ADC_ALC2 0x2a
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#define ES8316_ADC_ALC3 0x2b
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#define ES8316_ADC_ALC4 0x2c
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#define ES8316_ADC_ALC5 0x2d
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#define ES8316_ADC_ALC_NG 0x2e
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/* DAC Control */
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#define ES8316_DAC_PDN 0x2f
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#define ES8316_DAC_SET1 0x30
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#define ES8316_DAC_SET2 0x31
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#define ES8316_DAC_SET3 0x32
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#define ES8316_DAC_VOLL 0x33
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#define ES8316_DAC_VOLR 0x34
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/* GPIO */
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#define ES8316_GPIO_SEL 0x4d
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#define ES8316_GPIO_DEBOUNCE 0x4e
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#define ES8316_GPIO_FLAG 0x4f
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/* Test mode */
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#define ES8316_TESTMODE 0x50
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#define ES8316_TEST1 0x51
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#define ES8316_TEST2 0x52
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#define ES8316_TEST3 0x53
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/*
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* Field definitions
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*/
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/* ES8316_RESET */
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#define ES8316_RESET_CSM_ON 0x80
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/* ES8316_CLKMGR_CLKSW */
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#define ES8316_CLKMGR_CLKSW_MCLK_ON 0x40
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#define ES8316_CLKMGR_CLKSW_BCLK_ON 0x20
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/* ES8316_SERDATA1 */
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#define ES8316_SERDATA1_MASTER 0x80
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#define ES8316_SERDATA1_BCLK_INV 0x20
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/* ES8316_SERDATA_ADC and _DAC */
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#define ES8316_SERDATA2_FMT_MASK 0x3
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#define ES8316_SERDATA2_FMT_I2S 0x00
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#define ES8316_SERDATA2_FMT_LEFTJ 0x01
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#define ES8316_SERDATA2_FMT_RIGHTJ 0x02
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#define ES8316_SERDATA2_FMT_PCM 0x03
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#define ES8316_SERDATA2_ADCLRP 0x20
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#define ES8316_SERDATA2_LEN_MASK 0x1c
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#define ES8316_SERDATA2_LEN_24 0x00
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#define ES8316_SERDATA2_LEN_20 0x04
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#define ES8316_SERDATA2_LEN_18 0x08
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#define ES8316_SERDATA2_LEN_16 0x0c
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#define ES8316_SERDATA2_LEN_32 0x10
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/* ES8316_GPIO_DEBOUNCE */
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#define ES8316_GPIO_ENABLE_INTERRUPT 0x02
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/* ES8316_GPIO_FLAG */
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#define ES8316_GPIO_FLAG_GM_NOT_SHORTED 0x02
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#define ES8316_GPIO_FLAG_HP_NOT_INSERTED 0x04
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/* ES8316_CLKMGR_CLKSW */
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#define ES8316_CLKMGR_CLKSW_MCLK_DIV 0x80
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#endif
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