Geert Uytterhoeven e224396bf2 clk: renesas: r8a779f0: Fix RSW2 clock divider ... [ Upstream commit 691419f90f ] According to Section 8.1.2 Figure 8.1.1 ("Block Diagram of CPG"), Note 22 ("RSW2 divider"), and Table 8.1.4d ("Lists of CPG clocks generated from CPGMA1"), the RSwitch2 and PCI Express clock is generated from PLL5 by dividing by two, followed by the RSW2 divider. As PLL5 runs at 3200 MHz, and RSW2 is fixed to 320 MHz, the RSW2 divider must be 5. Correct the parent and the fixed divider. Fixes: 24aaff6a6c ("clk: renesas: cpg-mssr: Add support for R-Car S4-8") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d6a406f31e6f02f892e0253f4e8a9a2f68fd652e.1641566003.git.geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-04-08 13:58:25 +02:00
..
clk-div6.c	clk: renesas: div6: Implement range checking	2021-05-11 09:58:13 +02:00
clk-div6.h
clk-emev2.c
clk-mstp.c	clk: renesas: Zero init clk_init_data	2021-03-30 09:58:27 +02:00
clk-r8a73a4.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-r8a7740.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-r8a7778.c
clk-r8a7779.c
clk-rz.c	remove ioremap_nocache and devm_ioremap_nocache	2020-01-06 09:45:59 +01:00
clk-sh73a0.c	clk: renesas: sh73a0: Stop using __raw_*() I/O accessors	2020-12-10 08:34:01 +01:00
Kconfig	clk: renesas: cpg-mssr: Add support for R-Car S4-8	2021-12-08 10:05:56 +01:00
Makefile	clk: renesas: cpg-mssr: Add support for R-Car S4-8	2021-12-08 10:05:56 +01:00
r7s9210-cpg-mssr.c	clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag	2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a774b1-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a774c0-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a774e1-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a779a0-cpg-mssr.c	clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver	2021-12-08 10:05:22 +01:00
r8a779f0-cpg-mssr.c	clk: renesas: r8a779f0: Fix RSW2 clock divider	2022-04-08 13:58:25 +02:00
r8a7742-cpg-mssr.c	clk: renesas: r8a7742: Add clk entry for VSPR	2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a7796-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a77470-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a77970-cpg-mssr.c	clk: renesas: rcar-gen3: Mark RWDT clocks as critical	2020-06-22 16:53:49 +02:00
r8a77980-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a77990-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r8a77995-cpg-mssr.c	clk: renesas: rcar-gen3: Add SDnH clock	2021-11-19 11:27:58 +01:00
r9a06g032-clocks.c	clk: renesas: r9a06g032: Switch to .determine_rate()	2021-05-11 10:00:40 +02:00
r9a07g044-cpg.c	clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3	2022-04-08 13:58:23 +02:00
rcar-cpg-lib.c	clk: renesas: rcar-gen3: Switch to new SD clock handling	2021-11-19 11:32:39 +01:00
rcar-cpg-lib.h	clk: renesas: rcar-gen3: Switch to new SD clock handling	2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c	clk: renesas: Zero init clk_init_data	2021-03-30 09:58:27 +02:00
rcar-gen2-cpg.h	clk: renesas: rcar-gen2: Change multipliers and dividers to u8	2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c	clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST	2021-11-19 11:32:39 +01:00
rcar-gen3-cpg.h	clk: renesas: rcar-gen3: Add dummy SDnH clock	2021-11-19 11:27:58 +01:00
rcar-gen4-cpg.c	clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver	2021-12-08 10:05:22 +01:00
rcar-gen4-cpg.h	clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver	2021-12-08 10:05:22 +01:00
rcar-usb2-clock-sel.c	clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereference	2021-08-28 21:29:36 -07:00
renesas-cpg-mssr.c	clk: renesas: cpg-mssr: Add support for R-Car S4-8	2021-12-08 10:05:56 +01:00
renesas-cpg-mssr.h	clk: renesas: cpg-mssr: Add support for R-Car S4-8	2021-12-08 10:05:56 +01:00
rzg2l-cpg.c	clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()	2021-11-19 11:37:03 +01:00
rzg2l-cpg.h	clk: renesas: r9a07g044: Add mux and divider for G clock	2021-12-08 10:05:56 +01:00