Emil Renner Berthing f6ea015f96 clk: starfive: jh7100: Handle audio_div clock properly ... [ Upstream commit 73bfc8d745 ] It turns out the audio_div clock is a fractional divider where the lowest byte of the ctrl register is the integer part of the divider and the 2nd byte is the number of 100th added to the divider. The children of this clock is used by the audio peripherals for their sample rate clock, so round to the closest possible rate rather than always rounding down like regular dividers. Fixes: 4210be668a ("clk: starfive: Add JH7100 clock generator driver") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220126173953.1016706-3-kernel@esmil.dk Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-04-08 13:58:27 +02:00
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clk-starfive-jh7100.c	clk: starfive: jh7100: Handle audio_div clock properly	2022-04-08 13:58:27 +02:00
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