linux-stable/arch/riscv/errata/sifive/errata_cip_453.S
Vincent Chen 800149a77c
riscv: sifive: Apply errata "cip-453" patch
Add sign extension to the $badaddr before addressing the instruction page
fault and instruction access fault to workaround the issue "cip-453".

To avoid affecting the existing code sequence, this patch will creates two
trampolines to add sign extension to the $badaddr. By the "alternative"
mechanism, these two trampolines will replace the original exception
handler of instruction page fault and instruction access fault in the
excp_vect_table. In this case, only the specific SiFive CPU core jumps to
the do_page_fault and do_trap_insn_fault through these two trampolines.
Other CPUs are not affected.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-04-26 08:24:57 -07:00

38 lines
799 B
ArmAsm

/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2021 SiFive
*/
#include <linux/linkage.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/alternative.h>
.macro ADD_SIGN_EXT pt_reg badaddr tmp_reg
REG_L \badaddr, PT_BADADDR(\pt_reg)
li \tmp_reg,1
slli \tmp_reg,\tmp_reg,0x26
and \tmp_reg,\tmp_reg,\badaddr
beqz \tmp_reg, 1f
li \tmp_reg,-1
slli \tmp_reg,\tmp_reg,0x27
or \badaddr,\tmp_reg,\badaddr
REG_S \badaddr, PT_BADADDR(\pt_reg)
1:
.endm
ENTRY(sifive_cip_453_page_fault_trp)
ADD_SIGN_EXT a0, t0, t1
#ifdef CONFIG_MMU
la t0, do_page_fault
#else
la t0, do_trap_unknown
#endif
jr t0
END(sifive_cip_453_page_fault_trp)
ENTRY(sifive_cip_453_insn_fault_trp)
ADD_SIGN_EXT a0, t0, t1
la t0, do_trap_insn_fault
jr t0
END(sifive_cip_453_insn_fault_trp)