mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-11-01 17:08:10 +00:00
e8069f5a8e
* Eager page splitting optimization for dirty logging, optionally
allowing for a VM to avoid the cost of hugepage splitting in the stage-2
fault path.
* Arm FF-A proxy for pKVM, allowing a pKVM host to safely interact with
services that live in the Secure world. pKVM intervenes on FF-A calls
to guarantee the host doesn't misuse memory donated to the hyp or a
pKVM guest.
* Support for running the split hypervisor with VHE enabled, known as
'hVHE' mode. This is extremely useful for testing the split
hypervisor on VHE-only systems, and paves the way for new use cases
that depend on having two TTBRs available at EL2.
* Generalized framework for configurable ID registers from userspace.
KVM/arm64 currently prevents arbitrary CPU feature set configuration
from userspace, but the intent is to relax this limitation and allow
userspace to select a feature set consistent with the CPU.
* Enable the use of Branch Target Identification (FEAT_BTI) in the
hypervisor.
* Use a separate set of pointer authentication keys for the hypervisor
when running in protected mode, as the host is untrusted at runtime.
* Ensure timer IRQs are consistently released in the init failure
paths.
* Avoid trapping CTR_EL0 on systems with Enhanced Virtualization Traps
(FEAT_EVT), as it is a register commonly read from userspace.
* Erratum workaround for the upcoming AmpereOne part, which has broken
hardware A/D state management.
RISC-V:
* Redirect AMO load/store misaligned traps to KVM guest
* Trap-n-emulate AIA in-kernel irqchip for KVM guest
* Svnapot support for KVM Guest
s390:
* New uvdevice secret API
* CMM selftest and fixes
* fix racy access to target CPU for diag 9c
x86:
* Fix missing/incorrect #GP checks on ENCLS
* Use standard mmu_notifier hooks for handling APIC access page
* Drop now unnecessary TR/TSS load after VM-Exit on AMD
* Print more descriptive information about the status of SEV and SEV-ES during
module load
* Add a test for splitting and reconstituting hugepages during and after
dirty logging
* Add support for CPU pinning in demand paging test
* Add support for AMD PerfMonV2, with a variety of cleanups and minor fixes
included along the way
* Add a "nx_huge_pages=never" option to effectively avoid creating NX hugepage
recovery threads (because nx_huge_pages=off can be toggled at runtime)
* Move handling of PAT out of MTRR code and dedup SVM+VMX code
* Fix output of PIC poll command emulation when there's an interrupt
* Add a maintainer's handbook to document KVM x86 processes, preferred coding
style, testing expectations, etc.
* Misc cleanups, fixes and comments
Generic:
* Miscellaneous bugfixes and cleanups
Selftests:
* Generate dependency files so that partial rebuilds work as expected
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm updates from Paolo Bonzini:
"ARM64:
- Eager page splitting optimization for dirty logging, optionally
allowing for a VM to avoid the cost of hugepage splitting in the
stage-2 fault path.
- Arm FF-A proxy for pKVM, allowing a pKVM host to safely interact
with services that live in the Secure world. pKVM intervenes on
FF-A calls to guarantee the host doesn't misuse memory donated to
the hyp or a pKVM guest.
- Support for running the split hypervisor with VHE enabled, known as
'hVHE' mode. This is extremely useful for testing the split
hypervisor on VHE-only systems, and paves the way for new use cases
that depend on having two TTBRs available at EL2.
- Generalized framework for configurable ID registers from userspace.
KVM/arm64 currently prevents arbitrary CPU feature set
configuration from userspace, but the intent is to relax this
limitation and allow userspace to select a feature set consistent
with the CPU.
- Enable the use of Branch Target Identification (FEAT_BTI) in the
hypervisor.
- Use a separate set of pointer authentication keys for the
hypervisor when running in protected mode, as the host is untrusted
at runtime.
- Ensure timer IRQs are consistently released in the init failure
paths.
- Avoid trapping CTR_EL0 on systems with Enhanced Virtualization
Traps (FEAT_EVT), as it is a register commonly read from userspace.
- Erratum workaround for the upcoming AmpereOne part, which has
broken hardware A/D state management.
RISC-V:
- Redirect AMO load/store misaligned traps to KVM guest
- Trap-n-emulate AIA in-kernel irqchip for KVM guest
- Svnapot support for KVM Guest
s390:
- New uvdevice secret API
- CMM selftest and fixes
- fix racy access to target CPU for diag 9c
x86:
- Fix missing/incorrect #GP checks on ENCLS
- Use standard mmu_notifier hooks for handling APIC access page
- Drop now unnecessary TR/TSS load after VM-Exit on AMD
- Print more descriptive information about the status of SEV and
SEV-ES during module load
- Add a test for splitting and reconstituting hugepages during and
after dirty logging
- Add support for CPU pinning in demand paging test
- Add support for AMD PerfMonV2, with a variety of cleanups and minor
fixes included along the way
- Add a "nx_huge_pages=never" option to effectively avoid creating NX
hugepage recovery threads (because nx_huge_pages=off can be toggled
at runtime)
- Move handling of PAT out of MTRR code and dedup SVM+VMX code
- Fix output of PIC poll command emulation when there's an interrupt
- Add a maintainer's handbook to document KVM x86 processes,
preferred coding style, testing expectations, etc.
- Misc cleanups, fixes and comments
Generic:
- Miscellaneous bugfixes and cleanups
Selftests:
- Generate dependency files so that partial rebuilds work as
expected"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (153 commits)
Documentation/process: Add a maintainer handbook for KVM x86
Documentation/process: Add a label for the tip tree handbook's coding style
KVM: arm64: Fix misuse of KVM_ARM_VCPU_POWER_OFF bit index
RISC-V: KVM: Remove unneeded semicolon
RISC-V: KVM: Allow Svnapot extension for Guest/VM
riscv: kvm: define vcpu_sbi_ext_pmu in header
RISC-V: KVM: Expose IMSIC registers as attributes of AIA irqchip
RISC-V: KVM: Add in-kernel virtualization of AIA IMSIC
RISC-V: KVM: Expose APLIC registers as attributes of AIA irqchip
RISC-V: KVM: Add in-kernel emulation of AIA APLIC
RISC-V: KVM: Implement device interface for AIA irqchip
RISC-V: KVM: Skeletal in-kernel AIA irqchip support
RISC-V: KVM: Set kvm_riscv_aia_nr_hgei to zero
RISC-V: KVM: Add APLIC related defines
RISC-V: KVM: Add IMSIC related defines
RISC-V: KVM: Implement guest external interrupt line management
KVM: x86: Remove PRIx* definitions as they are solely for user space
s390/uv: Update query for secret-UVCs
s390/uv: replace scnprintf with sysfs_emit
s390/uvdevice: Add 'Lock Secret Store' UVC
...
516 lines
14 KiB
C
516 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CSR_H
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#define _ASM_RISCV_CSR_H
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#include <asm/asm.h>
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#include <linux/bits.h>
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/* Status register flags */
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#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
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#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
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#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
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#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
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#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
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#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
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#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
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#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
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#define SR_FS_OFF _AC(0x00000000, UL)
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#define SR_FS_INITIAL _AC(0x00002000, UL)
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#define SR_FS_CLEAN _AC(0x00004000, UL)
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#define SR_FS_DIRTY _AC(0x00006000, UL)
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#define SR_VS _AC(0x00000600, UL) /* Vector Status */
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#define SR_VS_OFF _AC(0x00000000, UL)
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#define SR_VS_INITIAL _AC(0x00000200, UL)
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#define SR_VS_CLEAN _AC(0x00000400, UL)
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#define SR_VS_DIRTY _AC(0x00000600, UL)
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#define SR_XS _AC(0x00018000, UL) /* Extension Status */
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#define SR_XS_OFF _AC(0x00000000, UL)
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#define SR_XS_INITIAL _AC(0x00008000, UL)
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#define SR_XS_CLEAN _AC(0x00010000, UL)
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#define SR_XS_DIRTY _AC(0x00018000, UL)
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#define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */
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#ifndef CONFIG_64BIT
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#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */
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#else
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#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
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#endif
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#ifdef CONFIG_64BIT
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#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */
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#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */
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#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */
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#endif
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/* SATP flags */
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#ifndef CONFIG_64BIT
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#define SATP_PPN _AC(0x003FFFFF, UL)
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#define SATP_MODE_32 _AC(0x80000000, UL)
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#define SATP_ASID_BITS 9
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#define SATP_ASID_SHIFT 22
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#define SATP_ASID_MASK _AC(0x1FF, UL)
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#else
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#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
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#define SATP_MODE_39 _AC(0x8000000000000000, UL)
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#define SATP_MODE_48 _AC(0x9000000000000000, UL)
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#define SATP_MODE_57 _AC(0xa000000000000000, UL)
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#define SATP_ASID_BITS 16
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#define SATP_ASID_SHIFT 44
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#define SATP_ASID_MASK _AC(0xFFFF, UL)
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#endif
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/* Exception cause high bit - is an interrupt if set */
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#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
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/* Interrupt causes (minus the high bit) */
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#define IRQ_S_SOFT 1
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#define IRQ_VS_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_VS_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_VS_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_S_GEXT 12
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#define IRQ_PMU_OVF 13
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#define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
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#define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)
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/* Exception causes */
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#define EXC_INST_MISALIGNED 0
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#define EXC_INST_ACCESS 1
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#define EXC_INST_ILLEGAL 2
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#define EXC_BREAKPOINT 3
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#define EXC_LOAD_MISALIGNED 4
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#define EXC_LOAD_ACCESS 5
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#define EXC_STORE_MISALIGNED 6
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#define EXC_STORE_ACCESS 7
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#define EXC_SYSCALL 8
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#define EXC_HYPERVISOR_SYSCALL 9
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#define EXC_SUPERVISOR_SYSCALL 10
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#define EXC_INST_PAGE_FAULT 12
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#define EXC_LOAD_PAGE_FAULT 13
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#define EXC_STORE_PAGE_FAULT 15
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#define EXC_INST_GUEST_PAGE_FAULT 20
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#define EXC_LOAD_GUEST_PAGE_FAULT 21
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#define EXC_VIRTUAL_INST_FAULT 22
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#define EXC_STORE_GUEST_PAGE_FAULT 23
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/* PMP configuration */
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#define PMP_R 0x01
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#define PMP_W 0x02
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#define PMP_X 0x04
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#define PMP_A 0x18
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#define PMP_A_TOR 0x08
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#define PMP_A_NA4 0x10
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#define PMP_A_NAPOT 0x18
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#define PMP_L 0x80
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/* HSTATUS flags */
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#ifdef CONFIG_64BIT
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#define HSTATUS_VSXL _AC(0x300000000, UL)
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#define HSTATUS_VSXL_SHIFT 32
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#endif
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#define HSTATUS_VTSR _AC(0x00400000, UL)
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#define HSTATUS_VTW _AC(0x00200000, UL)
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#define HSTATUS_VTVM _AC(0x00100000, UL)
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#define HSTATUS_VGEIN _AC(0x0003f000, UL)
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#define HSTATUS_VGEIN_SHIFT 12
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#define HSTATUS_HU _AC(0x00000200, UL)
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#define HSTATUS_SPVP _AC(0x00000100, UL)
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#define HSTATUS_SPV _AC(0x00000080, UL)
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#define HSTATUS_GVA _AC(0x00000040, UL)
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#define HSTATUS_VSBE _AC(0x00000020, UL)
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/* HGATP flags */
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#define HGATP_MODE_OFF _AC(0, UL)
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#define HGATP_MODE_SV32X4 _AC(1, UL)
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#define HGATP_MODE_SV39X4 _AC(8, UL)
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#define HGATP_MODE_SV48X4 _AC(9, UL)
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#define HGATP_MODE_SV57X4 _AC(10, UL)
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#define HGATP32_MODE_SHIFT 31
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#define HGATP32_VMID_SHIFT 22
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#define HGATP32_VMID GENMASK(28, 22)
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#define HGATP32_PPN GENMASK(21, 0)
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#define HGATP64_MODE_SHIFT 60
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#define HGATP64_VMID_SHIFT 44
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#define HGATP64_VMID GENMASK(57, 44)
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#define HGATP64_PPN GENMASK(43, 0)
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#define HGATP_PAGE_SHIFT 12
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#ifdef CONFIG_64BIT
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#define HGATP_PPN HGATP64_PPN
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#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT
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#define HGATP_VMID HGATP64_VMID
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#define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT
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#else
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#define HGATP_PPN HGATP32_PPN
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#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT
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#define HGATP_VMID HGATP32_VMID
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#define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT
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#endif
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/* VSIP & HVIP relation */
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#define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT)
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#define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \
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(_AC(1, UL) << IRQ_S_TIMER) | \
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(_AC(1, UL) << IRQ_S_EXT))
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/* AIA CSR bits */
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#define TOPI_IID_SHIFT 16
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#define TOPI_IID_MASK GENMASK(11, 0)
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#define TOPI_IPRIO_MASK GENMASK(7, 0)
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#define TOPI_IPRIO_BITS 8
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#define TOPEI_ID_SHIFT 16
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#define TOPEI_ID_MASK GENMASK(10, 0)
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#define TOPEI_PRIO_MASK GENMASK(10, 0)
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#define ISELECT_IPRIO0 0x30
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#define ISELECT_IPRIO15 0x3f
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#define ISELECT_MASK GENMASK(8, 0)
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#define HVICTL_VTI BIT(30)
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#define HVICTL_IID GENMASK(27, 16)
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#define HVICTL_IID_SHIFT 16
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#define HVICTL_DPR BIT(9)
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#define HVICTL_IPRIOM BIT(8)
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#define HVICTL_IPRIO GENMASK(7, 0)
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/* xENVCFG flags */
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#define ENVCFG_STCE (_AC(1, ULL) << 63)
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#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
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#define ENVCFG_CBZE (_AC(1, UL) << 7)
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#define ENVCFG_CBCFE (_AC(1, UL) << 6)
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#define ENVCFG_CBIE_SHIFT 4
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#define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT)
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#define ENVCFG_CBIE_ILL _AC(0x0, UL)
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#define ENVCFG_CBIE_FLUSH _AC(0x1, UL)
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#define ENVCFG_CBIE_INV _AC(0x3, UL)
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#define ENVCFG_FIOM _AC(0x1, UL)
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/* symbolic CSR names: */
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_HPMCOUNTER3 0xc03
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#define CSR_HPMCOUNTER4 0xc04
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#define CSR_HPMCOUNTER5 0xc05
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#define CSR_HPMCOUNTER6 0xc06
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#define CSR_HPMCOUNTER7 0xc07
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#define CSR_HPMCOUNTER8 0xc08
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#define CSR_HPMCOUNTER9 0xc09
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#define CSR_HPMCOUNTER10 0xc0a
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#define CSR_HPMCOUNTER11 0xc0b
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#define CSR_HPMCOUNTER12 0xc0c
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#define CSR_HPMCOUNTER13 0xc0d
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#define CSR_HPMCOUNTER14 0xc0e
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#define CSR_HPMCOUNTER15 0xc0f
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#define CSR_HPMCOUNTER16 0xc10
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#define CSR_HPMCOUNTER17 0xc11
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#define CSR_HPMCOUNTER18 0xc12
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#define CSR_HPMCOUNTER19 0xc13
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#define CSR_HPMCOUNTER20 0xc14
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#define CSR_HPMCOUNTER21 0xc15
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#define CSR_HPMCOUNTER22 0xc16
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#define CSR_HPMCOUNTER23 0xc17
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#define CSR_HPMCOUNTER24 0xc18
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#define CSR_HPMCOUNTER25 0xc19
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#define CSR_HPMCOUNTER26 0xc1a
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#define CSR_HPMCOUNTER27 0xc1b
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#define CSR_HPMCOUNTER28 0xc1c
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#define CSR_HPMCOUNTER29 0xc1d
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#define CSR_HPMCOUNTER30 0xc1e
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#define CSR_HPMCOUNTER31 0xc1f
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_HPMCOUNTER3H 0xc83
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#define CSR_HPMCOUNTER4H 0xc84
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#define CSR_HPMCOUNTER5H 0xc85
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#define CSR_HPMCOUNTER6H 0xc86
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#define CSR_HPMCOUNTER7H 0xc87
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#define CSR_HPMCOUNTER8H 0xc88
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#define CSR_HPMCOUNTER9H 0xc89
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#define CSR_HPMCOUNTER10H 0xc8a
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#define CSR_HPMCOUNTER11H 0xc8b
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#define CSR_HPMCOUNTER12H 0xc8c
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#define CSR_HPMCOUNTER13H 0xc8d
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#define CSR_HPMCOUNTER14H 0xc8e
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#define CSR_HPMCOUNTER15H 0xc8f
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#define CSR_HPMCOUNTER16H 0xc90
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#define CSR_HPMCOUNTER17H 0xc91
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#define CSR_HPMCOUNTER18H 0xc92
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#define CSR_HPMCOUNTER19H 0xc93
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#define CSR_HPMCOUNTER20H 0xc94
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#define CSR_HPMCOUNTER21H 0xc95
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#define CSR_HPMCOUNTER22H 0xc96
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#define CSR_HPMCOUNTER23H 0xc97
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#define CSR_HPMCOUNTER24H 0xc98
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#define CSR_HPMCOUNTER25H 0xc99
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#define CSR_HPMCOUNTER26H 0xc9a
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#define CSR_HPMCOUNTER27H 0xc9b
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#define CSR_HPMCOUNTER28H 0xc9c
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#define CSR_HPMCOUNTER29H 0xc9d
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#define CSR_HPMCOUNTER30H 0xc9e
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#define CSR_HPMCOUNTER31H 0xc9f
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#define CSR_SSCOUNTOVF 0xda0
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#define CSR_SSTATUS 0x100
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SATP 0x180
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#define CSR_STIMECMP 0x14D
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#define CSR_STIMECMPH 0x15D
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/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
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#define CSR_SISELECT 0x150
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#define CSR_SIREG 0x151
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/* Supervisor-Level Interrupts (AIA) */
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#define CSR_STOPEI 0x15c
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#define CSR_STOPI 0xdb0
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/* Supervisor-Level High-Half CSRs (AIA) */
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#define CSR_SIEH 0x114
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#define CSR_SIPH 0x154
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#define CSR_VSSTATUS 0x200
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#define CSR_VSIE 0x204
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#define CSR_VSTVEC 0x205
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#define CSR_VSSCRATCH 0x240
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#define CSR_VSEPC 0x241
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#define CSR_VSCAUSE 0x242
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#define CSR_VSTVAL 0x243
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#define CSR_VSIP 0x244
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#define CSR_VSATP 0x280
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#define CSR_VSTIMECMP 0x24D
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#define CSR_VSTIMECMPH 0x25D
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#define CSR_HSTATUS 0x600
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#define CSR_HEDELEG 0x602
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#define CSR_HIDELEG 0x603
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#define CSR_HIE 0x604
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#define CSR_HTIMEDELTA 0x605
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#define CSR_HCOUNTEREN 0x606
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#define CSR_HGEIE 0x607
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#define CSR_HENVCFG 0x60a
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#define CSR_HTIMEDELTAH 0x615
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#define CSR_HENVCFGH 0x61a
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#define CSR_HTVAL 0x643
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#define CSR_HIP 0x644
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#define CSR_HVIP 0x645
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#define CSR_HTINST 0x64a
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#define CSR_HGATP 0x680
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#define CSR_HGEIP 0xe12
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/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
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#define CSR_HVIEN 0x608
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#define CSR_HVICTL 0x609
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#define CSR_HVIPRIO1 0x646
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#define CSR_HVIPRIO2 0x647
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/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
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#define CSR_VSISELECT 0x250
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#define CSR_VSIREG 0x251
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/* VS-Level Interrupts (H-extension with AIA) */
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#define CSR_VSTOPEI 0x25c
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#define CSR_VSTOPI 0xeb0
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/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
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#define CSR_HIDELEGH 0x613
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#define CSR_HVIENH 0x618
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#define CSR_HVIPH 0x655
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#define CSR_HVIPRIO1H 0x656
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#define CSR_HVIPRIO2H 0x657
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#define CSR_VSIEH 0x214
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#define CSR_VSIPH 0x254
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MENVCFG 0x30a
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#define CSR_MENVCFGH 0x31a
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPADDR0 0x3b0
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#define CSR_MVENDORID 0xf11
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#define CSR_MARCHID 0xf12
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#define CSR_MIMPID 0xf13
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#define CSR_MHARTID 0xf14
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/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
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#define CSR_MISELECT 0x350
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#define CSR_MIREG 0x351
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/* Machine-Level Interrupts (AIA) */
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#define CSR_MTOPEI 0x35c
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#define CSR_MTOPI 0xfb0
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/* Virtual Interrupts for Supervisor Level (AIA) */
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#define CSR_MVIEN 0x308
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#define CSR_MVIP 0x309
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/* Machine-Level High-Half CSRs (AIA) */
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#define CSR_MIDELEGH 0x313
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#define CSR_MIEH 0x314
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#define CSR_MVIENH 0x318
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#define CSR_MVIPH 0x319
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#define CSR_MIPH 0x354
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#define CSR_VSTART 0x8
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#define CSR_VCSR 0xf
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#define CSR_VL 0xc20
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#define CSR_VTYPE 0xc21
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#define CSR_VLENB 0xc22
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#ifdef CONFIG_RISCV_M_MODE
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# define CSR_STATUS CSR_MSTATUS
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# define CSR_IE CSR_MIE
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# define CSR_TVEC CSR_MTVEC
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# define CSR_SCRATCH CSR_MSCRATCH
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# define CSR_EPC CSR_MEPC
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# define CSR_CAUSE CSR_MCAUSE
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# define CSR_TVAL CSR_MTVAL
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# define CSR_IP CSR_MIP
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# define CSR_IEH CSR_MIEH
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# define CSR_ISELECT CSR_MISELECT
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# define CSR_IREG CSR_MIREG
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# define CSR_IPH CSR_MIPH
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# define CSR_TOPEI CSR_MTOPEI
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# define CSR_TOPI CSR_MTOPI
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# define SR_IE SR_MIE
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# define SR_PIE SR_MPIE
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# define SR_PP SR_MPP
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# define RV_IRQ_SOFT IRQ_M_SOFT
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# define RV_IRQ_TIMER IRQ_M_TIMER
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# define RV_IRQ_EXT IRQ_M_EXT
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#else /* CONFIG_RISCV_M_MODE */
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# define CSR_STATUS CSR_SSTATUS
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# define CSR_IE CSR_SIE
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# define CSR_TVEC CSR_STVEC
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# define CSR_SCRATCH CSR_SSCRATCH
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# define CSR_EPC CSR_SEPC
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# define CSR_CAUSE CSR_SCAUSE
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# define CSR_TVAL CSR_STVAL
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# define CSR_IP CSR_SIP
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# define CSR_IEH CSR_SIEH
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# define CSR_ISELECT CSR_SISELECT
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# define CSR_IREG CSR_SIREG
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# define CSR_IPH CSR_SIPH
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# define CSR_TOPEI CSR_STOPEI
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# define CSR_TOPI CSR_STOPI
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# define SR_IE SR_SIE
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# define SR_PIE SR_SPIE
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# define SR_PP SR_SPP
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# define RV_IRQ_SOFT IRQ_S_SOFT
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# define RV_IRQ_TIMER IRQ_S_TIMER
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# define RV_IRQ_EXT IRQ_S_EXT
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# define RV_IRQ_PMU IRQ_PMU_OVF
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# define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF)
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#endif /* !CONFIG_RISCV_M_MODE */
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/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
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#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
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#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
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#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
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#ifndef __ASSEMBLY__
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#define csr_swap(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
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: "=r" (__v) : \
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: "memory"); \
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__v; \
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})
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#define csr_write(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_read_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_read_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_CSR_H */
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