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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ab0f77465e
Using memset() to zero a 4K page takes 563 total instructions, where 20 are branches. clear_page(), with Zicboz and a 64 byte block size, takes 169 total instructions, where 4 are branches and 33 are nops. Even though the block size is a variable, thanks to alternatives, we can still implement a Duff device without having to do any preliminary calculations. This is achieved by using the alternatives' cpufeature value (the upper 16 bits of patch_id). The value used is the maximum zicboz block size order accepted at the patch site. This enables us to stop patching / unrolling when 4K bytes have been zeroed (we would loop and continue after 4K if the page size would be larger) For 4K pages, unrolling 16 times allows block sizes of 64 and 128 to only loop a few times and larger block sizes to not loop at all. Since cbo.zero doesn't take an offset, we also need an 'add' after each instruction, making the loop body 112 to 160 bytes. Hopefully this is small enough to not cause icache misses. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230224162631.405473-7-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
199 lines
5.6 KiB
C
199 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_INSN_DEF_H
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#define __ASM_INSN_DEF_H
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#include <asm/asm.h>
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#define INSN_R_FUNC7_SHIFT 25
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#define INSN_R_RS2_SHIFT 20
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#define INSN_R_RS1_SHIFT 15
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#define INSN_R_FUNC3_SHIFT 12
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#define INSN_R_RD_SHIFT 7
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#define INSN_R_OPCODE_SHIFT 0
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#define INSN_I_SIMM12_SHIFT 20
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#define INSN_I_RS1_SHIFT 15
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#define INSN_I_FUNC3_SHIFT 12
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#define INSN_I_RD_SHIFT 7
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#define INSN_I_OPCODE_SHIFT 0
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#ifdef __ASSEMBLY__
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#ifdef CONFIG_AS_HAS_INSN
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.macro insn_r, opcode, func3, func7, rd, rs1, rs2
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.insn r \opcode, \func3, \func7, \rd, \rs1, \rs2
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.endm
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.macro insn_i, opcode, func3, rd, rs1, simm12
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.insn i \opcode, \func3, \rd, \rs1, \simm12
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.endm
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#else
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#include <asm/gpr-num.h>
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.macro insn_r, opcode, func3, func7, rd, rs1, rs2
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.4byte ((\opcode << INSN_R_OPCODE_SHIFT) | \
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(\func3 << INSN_R_FUNC3_SHIFT) | \
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(\func7 << INSN_R_FUNC7_SHIFT) | \
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(.L__gpr_num_\rd << INSN_R_RD_SHIFT) | \
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(.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \
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(.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT))
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.endm
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.macro insn_i, opcode, func3, rd, rs1, simm12
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.4byte ((\opcode << INSN_I_OPCODE_SHIFT) | \
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(\func3 << INSN_I_FUNC3_SHIFT) | \
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(.L__gpr_num_\rd << INSN_I_RD_SHIFT) | \
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(.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) | \
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(\simm12 << INSN_I_SIMM12_SHIFT))
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.endm
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#endif
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#define __INSN_R(...) insn_r __VA_ARGS__
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#define __INSN_I(...) insn_i __VA_ARGS__
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#else /* ! __ASSEMBLY__ */
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#ifdef CONFIG_AS_HAS_INSN
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#define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \
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".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"
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#define __INSN_I(opcode, func3, rd, rs1, simm12) \
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".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
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#else
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#include <linux/stringify.h>
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#include <asm/gpr-num.h>
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#define DEFINE_INSN_R \
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__DEFINE_ASM_GPR_NUMS \
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" .macro insn_r, opcode, func3, func7, rd, rs1, rs2\n" \
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" .4byte ((\\opcode << " __stringify(INSN_R_OPCODE_SHIFT) ") |" \
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" (\\func3 << " __stringify(INSN_R_FUNC3_SHIFT) ") |" \
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" (\\func7 << " __stringify(INSN_R_FUNC7_SHIFT) ") |" \
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" (.L__gpr_num_\\rd << " __stringify(INSN_R_RD_SHIFT) ") |" \
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" (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |" \
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" (.L__gpr_num_\\rs2 << " __stringify(INSN_R_RS2_SHIFT) "))\n" \
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" .endm\n"
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#define DEFINE_INSN_I \
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__DEFINE_ASM_GPR_NUMS \
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" .macro insn_i, opcode, func3, rd, rs1, simm12\n" \
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" .4byte ((\\opcode << " __stringify(INSN_I_OPCODE_SHIFT) ") |" \
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" (\\func3 << " __stringify(INSN_I_FUNC3_SHIFT) ") |" \
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" (.L__gpr_num_\\rd << " __stringify(INSN_I_RD_SHIFT) ") |" \
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" (.L__gpr_num_\\rs1 << " __stringify(INSN_I_RS1_SHIFT) ") |" \
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" (\\simm12 << " __stringify(INSN_I_SIMM12_SHIFT) "))\n" \
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" .endm\n"
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#define UNDEFINE_INSN_R \
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" .purgem insn_r\n"
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#define UNDEFINE_INSN_I \
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" .purgem insn_i\n"
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#define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \
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DEFINE_INSN_R \
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"insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \
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UNDEFINE_INSN_R
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#define __INSN_I(opcode, func3, rd, rs1, simm12) \
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DEFINE_INSN_I \
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"insn_i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" \
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UNDEFINE_INSN_I
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#endif
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#endif /* ! __ASSEMBLY__ */
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#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \
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__INSN_R(RV_##opcode, RV_##func3, RV_##func7, \
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RV_##rd, RV_##rs1, RV_##rs2)
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#define INSN_I(opcode, func3, rd, rs1, simm12) \
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__INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
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RV_##rs1, RV_##simm12)
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#define RV_OPCODE(v) __ASM_STR(v)
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#define RV_FUNC3(v) __ASM_STR(v)
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#define RV_FUNC7(v) __ASM_STR(v)
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#define RV_SIMM12(v) __ASM_STR(v)
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#define RV_RD(v) __ASM_STR(v)
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#define RV_RS1(v) __ASM_STR(v)
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#define RV_RS2(v) __ASM_STR(v)
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#define __RV_REG(v) __ASM_STR(x ## v)
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#define RV___RD(v) __RV_REG(v)
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#define RV___RS1(v) __RV_REG(v)
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#define RV___RS2(v) __RV_REG(v)
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#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
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#define RV_OPCODE_SYSTEM RV_OPCODE(115)
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#define HFENCE_VVMA(vaddr, asid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17), \
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__RD(0), RS1(vaddr), RS2(asid))
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#define HFENCE_GVMA(gaddr, vmid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \
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__RD(0), RS1(gaddr), RS2(vmid))
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#define HLVX_HU(dest, addr) \
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INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50), \
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RD(dest), RS1(addr), __RS2(3))
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#define HLV_W(dest, addr) \
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INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52), \
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RD(dest), RS1(addr), __RS2(0))
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#ifdef CONFIG_64BIT
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#define HLV_D(dest, addr) \
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INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54), \
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RD(dest), RS1(addr), __RS2(0))
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#else
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#define HLV_D(dest, addr) \
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__ASM_STR(.error "hlv.d requires 64-bit support")
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#endif
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#define SINVAL_VMA(vaddr, asid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \
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__RD(0), RS1(vaddr), RS2(asid))
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#define SFENCE_W_INVAL() \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12), \
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__RD(0), __RS1(0), __RS2(0))
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#define SFENCE_INVAL_IR() \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12), \
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__RD(0), __RS1(0), __RS2(1))
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#define HINVAL_VVMA(vaddr, asid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(19), \
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__RD(0), RS1(vaddr), RS2(asid))
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#define HINVAL_GVMA(gaddr, vmid) \
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INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51), \
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__RD(0), RS1(gaddr), RS2(vmid))
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#define CBO_inval(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(0))
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#define CBO_clean(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(1))
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#define CBO_flush(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(2))
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#define CBO_zero(base) \
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INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
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RS1(base), SIMM12(4))
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#endif /* __ASM_INSN_DEF_H */
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