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Svpbmt (the S should be capitalized) is the
"Supervisor-mode: page-based memory types" extension
that specifies attributes for cacheability, idempotency
and ordering.
The relevant settings are done in special bits in PTEs:
Here is the svpbmt PTE format:
| 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
N MT RSW D A G U X W R V
^
Of the Reserved bits [63:54] in a leaf PTE, the high bit is already
allocated (as the N bit), so bits [62:61] are used as the MT (aka
MemType) field. This field specifies one of three memory types that
are close equivalents (or equivalent in effect) to the three main x86
and ARMv8 memory types - as shown in the following table.
RISC-V
Encoding &
MemType RISC-V Description
---------- ------------------------------------------------
00 - PMA Normal Cacheable, No change to implied PMA memory type
01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
11 - Rsvd Reserved for future standard use
As the extension will not be present on all implementations,
implement a method to handle cpufeatures via alternatives
to not incur runtime penalties on cpu variants not supporting
specific extensions and patch relevant code parts at runtime.
Co-developed-by: Wei Fu <wefu@redhat.com>
Signed-off-by: Wei Fu <wefu@redhat.com>
Co-developed-by: Liu Shaohua <liush@allwinnertech.com>
Signed-off-by: Liu Shaohua <liush@allwinnertech.com>
Co-developed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@kernel.org>
[moved to use the alternatives mechanism]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Link: https://lore.kernel.org/r/20220511192921.2223629-10-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
36 lines
987 B
C
36 lines
987 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_PGTABLE_32_H
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#define _ASM_RISCV_PGTABLE_32_H
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#include <asm-generic/pgtable-nopmd.h>
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#include <linux/bits.h>
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#include <linux/const.h>
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/* Size of region mapped by a page global directory */
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#define PGDIR_SHIFT 22
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#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE - 1))
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#define MAX_POSSIBLE_PHYSMEM_BITS 34
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/*
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* rv32 PTE format:
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* | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
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* PFN reserved for SW D A G U X W R V
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*/
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#define _PAGE_PFN_MASK GENMASK(31, 10)
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#define _PAGE_NOCACHE 0
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#define _PAGE_IO 0
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#define _PAGE_MTMASK 0
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/* Set of bits to preserve across pte_modify() */
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#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
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_PAGE_WRITE | _PAGE_EXEC | \
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_PAGE_USER | _PAGE_GLOBAL))
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#endif /* _ASM_RISCV_PGTABLE_32_H */
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