Sergey Matyukevich 1537bf26e2 perf: RISC-V: exclude invalid pmu counters from SBI calls ... SBI firmware may not provide information for some counters in response to SBI_EXT_PMU_COUNTER_GET_INFO call. Exclude such counters from the subsequent SBI requests. For this purpose use global mask to keep track of fully specified counters. Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20220830155306.301714-3-geomatsi@gmail.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-09-08 13:34:50 -07:00
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arm_pmu.h	drivers/perf: arm_pmu: Handle 47 bit counters	2022-03-08 13:32:48 +00:00
riscv_pmu.h	perf: RISC-V: exclude invalid pmu counters from SBI calls	2022-09-08 13:34:50 -07:00