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2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2016,2017 IBM Corporation.
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*/
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#ifndef __XIVE_INTERNAL_H
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#define __XIVE_INTERNAL_H
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/* Each CPU carry one of these with various per-CPU state */
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struct xive_cpu {
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#ifdef CONFIG_SMP
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/* HW irq number and data of IPI */
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u32 hw_ipi;
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struct xive_irq_data ipi_data;
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#endif /* CONFIG_SMP */
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int chip_id;
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/* Queue datas. Only one is populated */
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#define XIVE_MAX_QUEUES 8
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struct xive_q queue[XIVE_MAX_QUEUES];
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/*
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* Pending mask. Each bit corresponds to a priority that
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* potentially has pending interrupts.
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*/
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u8 pending_prio;
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/* Cache of HW CPPR */
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u8 cppr;
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};
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/* Backend ops */
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struct xive_ops {
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int (*populate_irq_data)(u32 hw_irq, struct xive_irq_data *data);
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int (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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void (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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void (*setup_cpu)(unsigned int cpu, struct xive_cpu *xc);
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void (*teardown_cpu)(unsigned int cpu, struct xive_cpu *xc);
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bool (*match)(struct device_node *np);
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void (*shutdown)(void);
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void (*update_pending)(struct xive_cpu *xc);
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void (*eoi)(u32 hw_irq);
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void (*sync_source)(u32 hw_irq);
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u64 (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
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#ifdef CONFIG_SMP
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int (*get_ipi)(unsigned int cpu, struct xive_cpu *xc);
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void (*put_ipi)(unsigned int cpu, struct xive_cpu *xc);
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#endif
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const char *name;
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};
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bool xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
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u8 max_prio);
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__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift);
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static inline u32 xive_alloc_order(u32 queue_shift)
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{
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return (queue_shift > PAGE_SHIFT) ? (queue_shift - PAGE_SHIFT) : 0;
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}
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extern bool xive_cmdline_disabled;
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#endif /* __XIVE_INTERNAL_H */
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