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f3d549dd5b
Rename all Tegra binding documentation according to the first or primary compatible value they describe. This provides a clear naming scheme for the files, and prevents any naming conflicts should future SoC versions require their own binding. Signed-off-by: Stephen Warren <swarren@nvidia.com>
40 lines
1.3 KiB
Text
40 lines
1.3 KiB
Text
NVIDIA Tegra GPIO controller
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Required properties:
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- compatible : "nvidia,tegra<chip>-gpio"
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- reg : Physical base address and length of the controller's registers.
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- interrupts : The interrupt outputs from the controller. For Tegra20,
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there should be 7 interrupts specified, and for Tegra30, there should
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be 8 interrupts specified.
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters:
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- bit 0 specifies polarity (0 for normal, 1 for inverted)
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- gpio-controller : Marks the device node as a GPIO controller.
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- #interrupt-cells : Should be 2.
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The first cell is the GPIO number.
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The second cell is used to specify flags:
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bits[3:0] trigger type and level flags:
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1 = low-to-high edge triggered.
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2 = high-to-low edge triggered.
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4 = active high level-sensitive.
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8 = active low level-sensitive.
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Valid combinations are 1, 2, 3, 4, 8.
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- interrupt-controller : Marks the device node as an interrupt controller.
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Example:
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra20-gpio";
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reg = < 0x6000d000 0x1000 >;
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interrupts = < 0 32 0x04
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0 33 0x04
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0 34 0x04
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0 35 0x04
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0 55 0x04
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0 87 0x04
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0 89 0x04 >;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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