mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-28 20:02:17 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
the normal collection of driver updates to support new SoCs, fix incorrect data, and convert various drivers to clk_hw based APIs. In the core, we allow clk_ops::init() to return an error code now so that we can fail clk registration if the callback does something like fail to allocate memory. We also add a new "terminate" clk_op so that things done in clk_ops::init() can be undone, e.g. free memory. We also spit out a warning now when critical clks fail to enable and we support changing clk rates and enable/disable state through debugfs when developers compile the kernel themselves. On the driver front, we get support for what seems like a lot of Qualcomm and NXP SoCs given that those vendors dominate the diffstat. There are a couple new drivers for Xilinx and Amlogic SoCs too. The updates are all small things like fixing the way glitch free muxes switch parents, avoiding div-by-zero problems, or fixing data like parent names. See the updates section below for more details. Finally, the "basic" clk types have been converted to support specifying parents with clk_hw pointers. This work includes an overhaul of the fixed-rate clk type to be more modern by using clk_hw APIs. Core: - Let clk_ops::init() return an error code - Add a clk_ops::terminate() callback to undo clk_ops::init() - Warn about critical clks that fail to enable or prepare - Support dangerous debugfs actions on clks with dead code New Drivers: - Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Add a driver for BCLK of Freescale SAI cores - Add cam, vpe and sgx clock support for TI dra7 - Add aess clock support for TI omap5 - Enable clks for CPUfreq on Allwinner A64 SoCs - Add Amlogic meson8b DDR clock controller - Add input clocks to Amlogic meson8b controllers - Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2 - i.MX8MP clk driver support Updates: - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs - Detect more PRMCU variants in ux500 driver - Adjust the composite clk type to new way of describing clk parents - Fixes for clk controllers on qcom msm8998 SoCs - Fix gmac main clock for TI dra7 - Move TI dra7-atl clock header to correct location - Fix hidden node name dependency on TI clkctrl clocks - Fix Amlogic meson8b mali clock update using the glitch free mux - Fix Amlogic pll driver division by zero at init - Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config symbols - Switch more i.MX clk drivers to clk_hw based APIs - Disable non-functional divider between pll4_audio_div and pll4_post_div on imx6q - Fix watchdog2 clock name typo in imx7ulp clock driver - Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M SoCs - Suppress bind attrs for i.MX8M clock driver - Add a big comment in imx8qxp-lpcg driver to tell why devm_platform_ioremap_resource() shouldn't be used for the driver - A correction on i.MX8MN usb1_ctrl parent clock setting -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl44cXMRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVK5RAA2RUSUv8VI8Yg5ppZjJsQaVfTFBe6/djt fToQ81J2vDorCGAhJQmPPBob8Ylxbw903k7480LYHxe3jghf9rA9NtiTEF/1F/YJ 6EebFMSppRo+UeUAHUp78VQmMS3xgVDyod9nfHacMKd1wM2GCPFW+Nlz/uc/Y6tC CEkeVIyRejatX0ZkNK8IhtQF5VGNXh//9DfWwPORJsJrXpJPLJLVkPC5xqfJaBTZ uh/y7VJnYvJ6Yw5fm5mhzGvwjevuR2jpej+pHnCVvTAn4reg5tXH982T/u5rf71T I+6QDpclCNRduz3HeYcLygDa5vSYlT/7A2eucAB+OURGFjN7dpaDf3nUgxwZOgv/ LSV4g83rAob3mRofLKSfTwh2B/cBl9YKvMrZljnABg1RpFl03PUEZx437hPyT0vP S3uXdrH1yQpY/GZ94G2nBaV7AYzEYp5DJD72bWVNlAhhScIdblc5ANUQya7dHQdp EWMecfqt8PnBwj2WqHUXlz9uFdLQVughyp7bxUtJeD1+x91a05+sk2guntA4Ao6S Xn7eBIElbAIgMVUmVroKGEtJoA2JTDzQj4xQ337lp9MKOGAuytf6HHja/lBSanbu xB4gjrTuFHIHOPiiYpuG3UIX+NVwQzCfRvUZqcv0mUCTGwLrs620wMrzadUGMmIF +ajwSdMmS2o= =UjXu -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There are a few changes to the core framework this time around, in addition to the normal collection of driver updates to support new SoCs, fix incorrect data, and convert various drivers to clk_hw based APIs. In the core, we allow clk_ops::init() to return an error code now so that we can fail clk registration if the callback does something like fail to allocate memory. We also add a new "terminate" clk_op so that things done in clk_ops::init() can be undone, e.g. free memory. We also spit out a warning now when critical clks fail to enable and we support changing clk rates and enable/disable state through debugfs when developers compile the kernel themselves. On the driver front, we get support for what seems like a lot of Qualcomm and NXP SoCs given that those vendors dominate the diffstat. There are a couple new drivers for Xilinx and Amlogic SoCs too. The updates are all small things like fixing the way glitch free muxes switch parents, avoiding div-by-zero problems, or fixing data like parent names. See the updates section below for more details. Finally, the "basic" clk types have been converted to support specifying parents with clk_hw pointers. This work includes an overhaul of the fixed-rate clk type to be more modern by using clk_hw APIs. Core: - Let clk_ops::init() return an error code - Add a clk_ops::terminate() callback to undo clk_ops::init() - Warn about critical clks that fail to enable or prepare - Support dangerous debugfs actions on clks with dead code New Drivers: - Support for Xilinx Versal platform clks - Display clk controller on qcom sc7180 - Video clk controller on qcom sc7180 - Graphics clk controller on qcom sc7180 - CPU PLLs for qcom msm8916 - Move qcom msm8974 gfx3d clk to RPM control - Display port clk support on qcom sdm845 SoCs - Global clk controller on qcom ipq6018 - Add a driver for BCLK of Freescale SAI cores - Add cam, vpe and sgx clock support for TI dra7 - Add aess clock support for TI omap5 - Enable clks for CPUfreq on Allwinner A64 SoCs - Add Amlogic meson8b DDR clock controller - Add input clocks to Amlogic meson8b controllers - Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2 - i.MX8MP clk driver support Updates: - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs - Detect more PRMCU variants in ux500 driver - Adjust the composite clk type to new way of describing clk parents - Fixes for clk controllers on qcom msm8998 SoCs - Fix gmac main clock for TI dra7 - Move TI dra7-atl clock header to correct location - Fix hidden node name dependency on TI clkctrl clocks - Fix Amlogic meson8b mali clock update using the glitch free mux - Fix Amlogic pll driver division by zero at init - Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config symbols - Switch more i.MX clk drivers to clk_hw based APIs - Disable non-functional divider between pll4_audio_div and pll4_post_div on imx6q - Fix watchdog2 clock name typo in imx7ulp clock driver - Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M SoCs - Suppress bind attrs for i.MX8M clock driver - Add a big comment in imx8qxp-lpcg driver to tell why devm_platform_ioremap_resource() shouldn't be used for the driver - A correction on i.MX8MN usb1_ctrl parent clock setting" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (140 commits) dt/bindings: clk: fsl,plldig: Drop 'bindings' from schema id clk: ls1028a: Fix warning on clamp() usage clk: qoriq: add ls1088a hwaccel clocks support clk: ls1028a: Add clock driver for Display output interface dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings clk: fsl-sai: new driver dt-bindings: clock: document the fsl-sai driver clk: composite: add _register_composite_pdata() variants clk: qcom: rpmh: Sort OF match table dt-bindings: fix warnings in validation of qcom,gcc.yaml dt-binding: fix compilation error of the example in qcom,gcc.yaml clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag clk: zynqmp: Fix divider calculation clk: zynqmp: Add support for get max divider clk: zynqmp: Warn user if clock user are more than allowed clk: zynqmp: Extend driver for versal dt-bindings: clock: Add bindings for versal clock driver clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock ...
365 lines
11 KiB
Text
365 lines
11 KiB
Text
# SPDX-License-Identifier: GPL-2.0
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config CLKDEV_LOOKUP
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bool
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select HAVE_CLK
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config HAVE_CLK_PREPARE
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bool
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config COMMON_CLK
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bool
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select HAVE_CLK_PREPARE
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select CLKDEV_LOOKUP
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select SRCU
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select RATIONAL
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---help---
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The common clock framework is a single definition of struct
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clk, useful across many platforms, as well as an
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implementation of the clock API in include/linux/clk.h.
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Architectures utilizing the common struct clk should select
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this option.
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menu "Common Clock Framework"
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depends on COMMON_CLK
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config COMMON_CLK_WM831X
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tristate "Clock driver for WM831x/2x PMICs"
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depends on MFD_WM831X
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---help---
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Supports the clocking subsystem of the WM831x/2x series of
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PMICs from Wolfson Microelectronics.
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source "drivers/clk/versatile/Kconfig"
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config CLK_HSDK
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bool "PLL Driver for HSDK platform"
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depends on OF || COMPILE_TEST
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---help---
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This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
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control.
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config COMMON_CLK_MAX77686
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tristate "Clock driver for Maxim 77620/77686/77802 MFD"
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depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
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---help---
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This driver supports Maxim 77620/77686/77802 crystal oscillator
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clock.
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config COMMON_CLK_MAX9485
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tristate "Maxim 9485 Programmable Clock Generator"
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depends on I2C
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help
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This driver supports Maxim 9485 Programmable Audio Clock Generator
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config COMMON_CLK_RK808
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tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
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depends on MFD_RK808
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---help---
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This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
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These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
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Clkout1 is always on, Clkout2 can off by control register.
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config COMMON_CLK_HI655X
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tristate "Clock driver for Hi655x" if EXPERT
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depends on (MFD_HI655X_PMIC || COMPILE_TEST)
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depends on REGMAP
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default MFD_HI655X_PMIC
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---help---
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This driver supports the hi655x PMIC clock. This
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multi-function device has one fixed-rate oscillator, clocked
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at 32KHz.
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config COMMON_CLK_SCMI
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tristate "Clock driver controlled via SCMI interface"
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depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
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---help---
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This driver provides support for clocks that are controlled
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by firmware that implements the SCMI interface.
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This driver uses SCMI Message Protocol to interact with the
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firmware providing all the clock controls.
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config COMMON_CLK_SCPI
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tristate "Clock driver controlled via SCPI interface"
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depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
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---help---
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This driver provides support for clocks that are controlled
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by firmware that implements the SCPI interface.
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This driver uses SCPI Message Protocol to interact with the
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firmware providing all the clock controls.
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config COMMON_CLK_SI5341
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tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
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depends on I2C
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select REGMAP_I2C
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help
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This driver supports Silicon Labs Si5341 and Si5340 programmable clock
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generators. Not all features of these chips are currently supported
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by the driver, in particular it only supports XTAL input. The chip can
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be pre-programmed to support other configurations and features not yet
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implemented in the driver.
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config COMMON_CLK_SI5351
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tristate "Clock driver for SiLabs 5351A/B/C"
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depends on I2C
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select REGMAP_I2C
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select RATIONAL
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---help---
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This driver supports Silicon Labs 5351A/B/C programmable clock
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generators.
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config COMMON_CLK_SI514
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tristate "Clock driver for SiLabs 514 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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This driver supports the Silicon Labs 514 programmable clock
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generator.
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config COMMON_CLK_SI544
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tristate "Clock driver for SiLabs 544 devices"
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depends on I2C
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select REGMAP_I2C
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help
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This driver supports the Silicon Labs 544 programmable clock
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generator.
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config COMMON_CLK_SI570
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tristate "Clock driver for SiLabs 570 and compatible devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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This driver supports Silicon Labs 570/571/598/599 programmable
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clock generators.
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config COMMON_CLK_BM1880
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bool "Clock driver for Bitmain BM1880 SoC"
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depends on ARCH_BITMAIN || COMPILE_TEST
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default ARCH_BITMAIN
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help
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This driver supports the clocks on Bitmain BM1880 SoC.
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config COMMON_CLK_CDCE706
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tristate "Clock driver for TI CDCE706 clock synthesizer"
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depends on I2C
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select REGMAP_I2C
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select RATIONAL
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---help---
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This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
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config COMMON_CLK_CDCE925
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tristate "Clock driver for TI CDCE913/925/937/949 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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This driver supports the TI CDCE913/925/937/949 programmable clock
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synthesizer. Each chip has different number of PLLs and outputs.
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For example, the CDCE925 contains two PLLs with spread-spectrum
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clocking support and five output dividers. The driver only supports
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the following setup, and uses a fixed setting for the output muxes.
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Y1 is derived from the input clock
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Y2 and Y3 derive from PLL1
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Y4 and Y5 derive from PLL2
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Given a target output frequency, the driver will set the PLL and
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divider to best approximate the desired output.
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config COMMON_CLK_CS2000_CP
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tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
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depends on I2C
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help
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If you say yes here you get support for the CS2000 clock multiplier.
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config COMMON_CLK_FSL_SAI
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bool "Clock driver for BCLK of Freescale SAI cores"
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depends on ARCH_LAYERSCAPE || COMPILE_TEST
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help
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This driver supports the Freescale SAI (Synchronous Audio Interface)
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to be used as a generic clock output. Some SoCs have restrictions
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regarding the possible pin multiplexer settings. Eg. on some SoCs
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two SAI interfaces can only be enabled together. If just one is
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needed, the BCLK pin of the second one can be used as general
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purpose clock output. Ideally, it can be used to drive an audio
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codec (sometimes known as MCLK).
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config COMMON_CLK_GEMINI
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bool "Clock driver for Cortina Systems Gemini SoC"
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depends on ARCH_GEMINI || COMPILE_TEST
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select MFD_SYSCON
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select RESET_CONTROLLER
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---help---
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This driver supports the SoC clocks on the Cortina Systems Gemini
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platform, also known as SL3516 or CS3516.
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config COMMON_CLK_ASPEED
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bool "Clock driver for Aspeed BMC SoCs"
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depends on ARCH_ASPEED || COMPILE_TEST
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default ARCH_ASPEED
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select MFD_SYSCON
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select RESET_CONTROLLER
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---help---
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This driver supports the SoC clocks on the Aspeed BMC platforms.
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The G4 and G5 series, including the ast2400 and ast2500, are supported
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by this driver.
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config COMMON_CLK_S2MPS11
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tristate "Clock driver for S2MPS1X/S5M8767 MFD"
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depends on MFD_SEC_CORE || COMPILE_TEST
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---help---
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This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
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clock. These multi-function devices have two (S2MPS14) or three
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(S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
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config CLK_TWL6040
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tristate "External McPDM functional clock from twl6040"
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depends on TWL6040_CORE
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---help---
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Enable the external functional clock support on OMAP4+ platforms for
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McPDM. McPDM module is using the external bit clock on the McPDM bus
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as functional clock.
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config COMMON_CLK_AXI_CLKGEN
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tristate "AXI clkgen driver"
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depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
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help
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Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
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FPGAs. It is commonly used in Analog Devices' reference designs.
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config CLK_QORIQ
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bool "Clock driver for Freescale QorIQ platforms"
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depends on (PPC_E500MC || ARM || ARM64 || COMPILE_TEST) && OF
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---help---
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This adds the clock driver support for Freescale QorIQ platforms
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using common clock framework.
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config CLK_LS1028A_PLLDIG
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tristate "Clock driver for LS1028A Display output"
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depends on ARCH_LAYERSCAPE || COMPILE_TEST
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default ARCH_LAYERSCAPE
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help
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This driver support the Display output interfaces(LCD, DPHY) pixel clocks
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of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
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features of the PLL are currently supported by the driver. By default,
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configured bypass mode with this PLL.
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config COMMON_CLK_XGENE
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bool "Clock driver for APM XGene SoC"
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default ARCH_XGENE
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depends on ARM64 || COMPILE_TEST
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---help---
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Sypport for the APM X-Gene SoC reference, PLL, and device clocks.
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config COMMON_CLK_LOCHNAGAR
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tristate "Cirrus Logic Lochnagar clock driver"
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depends on MFD_LOCHNAGAR
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help
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This driver supports the clocking features of the Cirrus Logic
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Lochnagar audio development board.
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config COMMON_CLK_NXP
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def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
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select REGMAP_MMIO if ARCH_LPC32XX
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select MFD_SYSCON if ARCH_LPC18XX
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---help---
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Support for clock providers on NXP platforms.
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config COMMON_CLK_PALMAS
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tristate "Clock driver for TI Palmas devices"
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depends on MFD_PALMAS
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---help---
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This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
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using common clock framework.
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config COMMON_CLK_PWM
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tristate "Clock driver for PWMs used as clock outputs"
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depends on PWM
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---help---
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Adapter driver so that any PWM output can be (mis)used as clock signal
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at 50% duty cycle.
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config COMMON_CLK_PXA
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def_bool COMMON_CLK && ARCH_PXA
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---help---
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Support for the Marvell PXA SoC.
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config COMMON_CLK_PIC32
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def_bool COMMON_CLK && MACH_PIC32
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config COMMON_CLK_OXNAS
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bool "Clock driver for the OXNAS SoC Family"
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depends on ARCH_OXNAS || COMPILE_TEST
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select MFD_SYSCON
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---help---
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Support for the OXNAS SoC Family clocks.
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config COMMON_CLK_VC5
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tristate "Clock driver for IDT VersaClock 5,6 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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This driver supports the IDT VersaClock 5 and VersaClock 6
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programmable clock generators.
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config COMMON_CLK_STM32MP157
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def_bool COMMON_CLK && MACH_STM32MP157
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help
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Support for stm32mp157 SoC family clocks
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config COMMON_CLK_STM32F
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def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
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help
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Support for stm32f4 and stm32f7 SoC families clocks
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config COMMON_CLK_STM32H7
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def_bool COMMON_CLK && MACH_STM32H743
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help
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Support for stm32h7 SoC family clocks
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config COMMON_CLK_MMP2
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def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
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help
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Support for Marvell MMP2 and MMP3 SoC clocks
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config COMMON_CLK_BD718XX
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tristate "Clock driver for 32K clk gates on ROHM PMICs"
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depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828
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help
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This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and
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ROHM BD70528 PMICs clock gates.
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config COMMON_CLK_FIXED_MMIO
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bool "Clock driver for Memory Mapped Fixed values"
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depends on COMMON_CLK && OF
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help
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Support for Memory Mapped IO Fixed clocks
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source "drivers/clk/actions/Kconfig"
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source "drivers/clk/analogbits/Kconfig"
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source "drivers/clk/bcm/Kconfig"
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source "drivers/clk/hisilicon/Kconfig"
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source "drivers/clk/imgtec/Kconfig"
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source "drivers/clk/imx/Kconfig"
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source "drivers/clk/ingenic/Kconfig"
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source "drivers/clk/keystone/Kconfig"
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source "drivers/clk/mediatek/Kconfig"
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source "drivers/clk/meson/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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source "drivers/clk/sifive/Kconfig"
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source "drivers/clk/sprd/Kconfig"
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source "drivers/clk/sunxi/Kconfig"
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source "drivers/clk/sunxi-ng/Kconfig"
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source "drivers/clk/tegra/Kconfig"
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source "drivers/clk/ti/Kconfig"
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source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/zynqmp/Kconfig"
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endmenu
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