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Fix inconsistent IS_ERR and PTR_ERR in imx8m_ddrc_probe(). Detected using Coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
471 lines
12 KiB
C
471 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/devfreq.h>
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#include <linux/pm_opp.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/arm-smccc.h>
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#define IMX_SIP_DDR_DVFS 0xc2000004
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/* Query available frequencies. */
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#define IMX_SIP_DDR_DVFS_GET_FREQ_COUNT 0x10
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#define IMX_SIP_DDR_DVFS_GET_FREQ_INFO 0x11
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/*
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* This should be in a 1:1 mapping with devicetree OPPs but
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* firmware provides additional info.
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*/
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struct imx8m_ddrc_freq {
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unsigned long rate;
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unsigned long smcarg;
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int dram_core_parent_index;
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int dram_alt_parent_index;
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int dram_apb_parent_index;
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};
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/* Hardware limitation */
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#define IMX8M_DDRC_MAX_FREQ_COUNT 4
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/*
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* i.MX8M DRAM Controller clocks have the following structure (abridged):
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*
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* +----------+ |\ +------+
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* | dram_pll |-------|M| dram_core | |
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* +----------+ |U|---------->| D |
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* /--|X| | D |
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* dram_alt_root | |/ | R |
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* | | C |
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* +---------+ | |
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* |FIX DIV/4| | |
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* +---------+ | |
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* composite: | | |
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* +----------+ | | |
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* | dram_alt |----/ | |
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* +----------+ | |
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* | dram_apb |-------------------->| |
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* +----------+ +------+
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*
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* The dram_pll is used for higher rates and dram_alt is used for lower rates.
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*
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* Frequency switching is implemented in TF-A (via SMC call) and can change the
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* configuration of the clocks, including mux parents. The dram_alt and
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* dram_apb clocks are "imx composite" and their parent can change too.
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*
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* We need to prepare/enable the new mux parents head of switching and update
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* their information afterwards.
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*/
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struct imx8m_ddrc {
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struct devfreq_dev_profile profile;
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struct devfreq *devfreq;
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/* For frequency switching: */
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struct clk *dram_core;
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struct clk *dram_pll;
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struct clk *dram_alt;
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struct clk *dram_apb;
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int freq_count;
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struct imx8m_ddrc_freq freq_table[IMX8M_DDRC_MAX_FREQ_COUNT];
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};
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static struct imx8m_ddrc_freq *imx8m_ddrc_find_freq(struct imx8m_ddrc *priv,
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unsigned long rate)
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{
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struct imx8m_ddrc_freq *freq;
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int i;
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/*
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* Firmware reports values in MT/s, so we round-down from Hz
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* Rounding is extra generous to ensure a match.
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*/
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rate = DIV_ROUND_CLOSEST(rate, 250000);
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for (i = 0; i < priv->freq_count; ++i) {
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freq = &priv->freq_table[i];
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if (freq->rate == rate ||
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freq->rate + 1 == rate ||
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freq->rate - 1 == rate)
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return freq;
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}
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return NULL;
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}
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static void imx8m_ddrc_smc_set_freq(int target_freq)
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{
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struct arm_smccc_res res;
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u32 online_cpus = 0;
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int cpu;
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local_irq_disable();
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for_each_online_cpu(cpu)
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online_cpus |= (1 << (cpu * 8));
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/* change the ddr freqency */
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arm_smccc_smc(IMX_SIP_DDR_DVFS, target_freq, online_cpus,
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0, 0, 0, 0, 0, &res);
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local_irq_enable();
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}
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static struct clk *clk_get_parent_by_index(struct clk *clk, int index)
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{
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struct clk_hw *hw;
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hw = clk_hw_get_parent_by_index(__clk_get_hw(clk), index);
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return hw ? hw->clk : NULL;
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}
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static int imx8m_ddrc_set_freq(struct device *dev, struct imx8m_ddrc_freq *freq)
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{
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struct imx8m_ddrc *priv = dev_get_drvdata(dev);
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struct clk *new_dram_core_parent;
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struct clk *new_dram_alt_parent;
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struct clk *new_dram_apb_parent;
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int ret;
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/*
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* Fetch new parents
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*
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* new_dram_alt_parent and new_dram_apb_parent are optional but
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* new_dram_core_parent is not.
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*/
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new_dram_core_parent = clk_get_parent_by_index(
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priv->dram_core, freq->dram_core_parent_index - 1);
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if (!new_dram_core_parent) {
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dev_err(dev, "failed to fetch new dram_core parent\n");
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return -EINVAL;
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}
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if (freq->dram_alt_parent_index) {
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new_dram_alt_parent = clk_get_parent_by_index(
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priv->dram_alt,
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freq->dram_alt_parent_index - 1);
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if (!new_dram_alt_parent) {
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dev_err(dev, "failed to fetch new dram_alt parent\n");
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return -EINVAL;
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}
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} else
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new_dram_alt_parent = NULL;
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if (freq->dram_apb_parent_index) {
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new_dram_apb_parent = clk_get_parent_by_index(
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priv->dram_apb,
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freq->dram_apb_parent_index - 1);
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if (!new_dram_apb_parent) {
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dev_err(dev, "failed to fetch new dram_apb parent\n");
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return -EINVAL;
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}
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} else
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new_dram_apb_parent = NULL;
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/* increase reference counts and ensure clks are ON before switch */
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ret = clk_prepare_enable(new_dram_core_parent);
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if (ret) {
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dev_err(dev, "failed to enable new dram_core parent: %d\n",
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ret);
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goto out;
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}
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ret = clk_prepare_enable(new_dram_alt_parent);
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if (ret) {
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dev_err(dev, "failed to enable new dram_alt parent: %d\n",
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ret);
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goto out_disable_core_parent;
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}
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ret = clk_prepare_enable(new_dram_apb_parent);
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if (ret) {
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dev_err(dev, "failed to enable new dram_apb parent: %d\n",
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ret);
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goto out_disable_alt_parent;
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}
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imx8m_ddrc_smc_set_freq(freq->smcarg);
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/* update parents in clk tree after switch. */
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ret = clk_set_parent(priv->dram_core, new_dram_core_parent);
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if (ret)
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dev_warn(dev, "failed to set dram_core parent: %d\n", ret);
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if (new_dram_alt_parent) {
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ret = clk_set_parent(priv->dram_alt, new_dram_alt_parent);
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if (ret)
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dev_warn(dev, "failed to set dram_alt parent: %d\n",
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ret);
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}
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if (new_dram_apb_parent) {
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ret = clk_set_parent(priv->dram_apb, new_dram_apb_parent);
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if (ret)
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dev_warn(dev, "failed to set dram_apb parent: %d\n",
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ret);
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}
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/*
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* Explicitly refresh dram PLL rate.
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*
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* Even if it's marked with CLK_GET_RATE_NOCACHE the rate will not be
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* automatically refreshed when clk_get_rate is called on children.
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*/
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clk_get_rate(priv->dram_pll);
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/*
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* clk_set_parent transfer the reference count from old parent.
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* now we drop extra reference counts used during the switch
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*/
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clk_disable_unprepare(new_dram_apb_parent);
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out_disable_alt_parent:
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clk_disable_unprepare(new_dram_alt_parent);
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out_disable_core_parent:
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clk_disable_unprepare(new_dram_core_parent);
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out:
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return ret;
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}
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static int imx8m_ddrc_target(struct device *dev, unsigned long *freq, u32 flags)
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{
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struct imx8m_ddrc *priv = dev_get_drvdata(dev);
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struct imx8m_ddrc_freq *freq_info;
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struct dev_pm_opp *new_opp;
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unsigned long old_freq, new_freq;
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int ret;
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new_opp = devfreq_recommended_opp(dev, freq, flags);
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if (IS_ERR(new_opp)) {
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ret = PTR_ERR(new_opp);
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dev_err(dev, "failed to get recommended opp: %d\n", ret);
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return ret;
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}
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dev_pm_opp_put(new_opp);
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old_freq = clk_get_rate(priv->dram_core);
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if (*freq == old_freq)
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return 0;
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freq_info = imx8m_ddrc_find_freq(priv, *freq);
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if (!freq_info)
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return -EINVAL;
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/*
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* Read back the clk rate to verify switch was correct and so that
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* we can report it on all error paths.
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*/
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ret = imx8m_ddrc_set_freq(dev, freq_info);
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new_freq = clk_get_rate(priv->dram_core);
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if (ret)
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dev_err(dev, "ddrc failed freq switch to %lu from %lu: error %d. now at %lu\n",
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*freq, old_freq, ret, new_freq);
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else if (*freq != new_freq)
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dev_err(dev, "ddrc failed freq update to %lu from %lu, now at %lu\n",
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*freq, old_freq, new_freq);
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else
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dev_dbg(dev, "ddrc freq set to %lu (was %lu)\n",
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*freq, old_freq);
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return ret;
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}
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static int imx8m_ddrc_get_cur_freq(struct device *dev, unsigned long *freq)
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{
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struct imx8m_ddrc *priv = dev_get_drvdata(dev);
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*freq = clk_get_rate(priv->dram_core);
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return 0;
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}
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static int imx8m_ddrc_get_dev_status(struct device *dev,
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struct devfreq_dev_status *stat)
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{
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struct imx8m_ddrc *priv = dev_get_drvdata(dev);
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stat->busy_time = 0;
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stat->total_time = 0;
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stat->current_frequency = clk_get_rate(priv->dram_core);
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return 0;
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}
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static int imx8m_ddrc_init_freq_info(struct device *dev)
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{
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struct imx8m_ddrc *priv = dev_get_drvdata(dev);
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struct arm_smccc_res res;
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int index;
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/* An error here means DDR DVFS API not supported by firmware */
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arm_smccc_smc(IMX_SIP_DDR_DVFS, IMX_SIP_DDR_DVFS_GET_FREQ_COUNT,
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0, 0, 0, 0, 0, 0, &res);
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priv->freq_count = res.a0;
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if (priv->freq_count <= 0 ||
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priv->freq_count > IMX8M_DDRC_MAX_FREQ_COUNT)
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return -ENODEV;
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for (index = 0; index < priv->freq_count; ++index) {
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struct imx8m_ddrc_freq *freq = &priv->freq_table[index];
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arm_smccc_smc(IMX_SIP_DDR_DVFS, IMX_SIP_DDR_DVFS_GET_FREQ_INFO,
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index, 0, 0, 0, 0, 0, &res);
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/* Result should be strictly positive */
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if ((long)res.a0 <= 0)
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return -ENODEV;
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freq->rate = res.a0;
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freq->smcarg = index;
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freq->dram_core_parent_index = res.a1;
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freq->dram_alt_parent_index = res.a2;
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freq->dram_apb_parent_index = res.a3;
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/* dram_core has 2 options: dram_pll or dram_alt_root */
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if (freq->dram_core_parent_index != 1 &&
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freq->dram_core_parent_index != 2)
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return -ENODEV;
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/* dram_apb and dram_alt have exactly 8 possible parents */
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if (freq->dram_alt_parent_index > 8 ||
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freq->dram_apb_parent_index > 8)
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return -ENODEV;
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/* dram_core from alt requires explicit dram_alt parent */
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if (freq->dram_core_parent_index == 2 &&
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freq->dram_alt_parent_index == 0)
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return -ENODEV;
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}
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return 0;
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}
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static int imx8m_ddrc_check_opps(struct device *dev)
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{
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struct imx8m_ddrc *priv = dev_get_drvdata(dev);
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struct imx8m_ddrc_freq *freq_info;
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struct dev_pm_opp *opp;
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unsigned long freq;
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int i, opp_count;
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/* Enumerate DT OPPs and disable those not supported by firmware */
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opp_count = dev_pm_opp_get_opp_count(dev);
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if (opp_count < 0)
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return opp_count;
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for (i = 0, freq = 0; i < opp_count; ++i, ++freq) {
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opp = dev_pm_opp_find_freq_ceil(dev, &freq);
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if (IS_ERR(opp)) {
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dev_err(dev, "Failed enumerating OPPs: %ld\n",
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PTR_ERR(opp));
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return PTR_ERR(opp);
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}
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dev_pm_opp_put(opp);
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freq_info = imx8m_ddrc_find_freq(priv, freq);
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if (!freq_info) {
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dev_info(dev, "Disable unsupported OPP %luHz %luMT/s\n",
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freq, DIV_ROUND_CLOSEST(freq, 250000));
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dev_pm_opp_disable(dev, freq);
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}
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}
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return 0;
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}
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static void imx8m_ddrc_exit(struct device *dev)
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{
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dev_pm_opp_of_remove_table(dev);
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}
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static int imx8m_ddrc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct imx8m_ddrc *priv;
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const char *gov = DEVFREQ_GOV_USERSPACE;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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platform_set_drvdata(pdev, priv);
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ret = imx8m_ddrc_init_freq_info(dev);
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if (ret) {
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dev_err(dev, "failed to init firmware freq info: %d\n", ret);
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return ret;
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}
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priv->dram_core = devm_clk_get(dev, "core");
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if (IS_ERR(priv->dram_core)) {
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ret = PTR_ERR(priv->dram_core);
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dev_err(dev, "failed to fetch core clock: %d\n", ret);
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return ret;
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}
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priv->dram_pll = devm_clk_get(dev, "pll");
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if (IS_ERR(priv->dram_pll)) {
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ret = PTR_ERR(priv->dram_pll);
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dev_err(dev, "failed to fetch pll clock: %d\n", ret);
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return ret;
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}
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priv->dram_alt = devm_clk_get(dev, "alt");
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if (IS_ERR(priv->dram_alt)) {
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ret = PTR_ERR(priv->dram_alt);
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dev_err(dev, "failed to fetch alt clock: %d\n", ret);
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return ret;
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}
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priv->dram_apb = devm_clk_get(dev, "apb");
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if (IS_ERR(priv->dram_apb)) {
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ret = PTR_ERR(priv->dram_apb);
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dev_err(dev, "failed to fetch apb clock: %d\n", ret);
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return ret;
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}
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ret = dev_pm_opp_of_add_table(dev);
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if (ret < 0) {
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dev_err(dev, "failed to get OPP table\n");
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return ret;
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}
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ret = imx8m_ddrc_check_opps(dev);
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if (ret < 0)
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goto err;
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priv->profile.polling_ms = 1000;
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priv->profile.target = imx8m_ddrc_target;
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priv->profile.get_dev_status = imx8m_ddrc_get_dev_status;
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priv->profile.exit = imx8m_ddrc_exit;
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priv->profile.get_cur_freq = imx8m_ddrc_get_cur_freq;
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priv->profile.initial_freq = clk_get_rate(priv->dram_core);
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priv->devfreq = devm_devfreq_add_device(dev, &priv->profile,
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gov, NULL);
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if (IS_ERR(priv->devfreq)) {
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ret = PTR_ERR(priv->devfreq);
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dev_err(dev, "failed to add devfreq device: %d\n", ret);
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goto err;
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}
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return 0;
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err:
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dev_pm_opp_of_remove_table(dev);
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return ret;
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}
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static const struct of_device_id imx8m_ddrc_of_match[] = {
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{ .compatible = "fsl,imx8m-ddrc", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, imx8m_ddrc_of_match);
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static struct platform_driver imx8m_ddrc_platdrv = {
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.probe = imx8m_ddrc_probe,
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.driver = {
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.name = "imx8m-ddrc-devfreq",
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.of_match_table = of_match_ptr(imx8m_ddrc_of_match),
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},
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};
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module_platform_driver(imx8m_ddrc_platdrv);
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MODULE_DESCRIPTION("i.MX8M DDR Controller frequency driver");
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MODULE_AUTHOR("Leonard Crestez <leonard.crestez@nxp.com>");
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MODULE_LICENSE("GPL v2");
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