mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-27 12:57:53 +00:00
54c2cc7919
Here is the "big" set of USB and Thunderbolt driver changes for
5.18-rc1. For the most part it's been a quiet development cycle for the
USB core, but there are the usual "hot spots" of development activity.
Included in here are:
- Thunderbolt driver updates:
- fixes for devices without displayport adapters
- lane bonding support and improvements
- other minor changes based on device testing
- dwc3 gadget driver changes. It seems this driver will never
be finished given that the IP core is showing up in zillions
of new devices and each implementation decides to do something
different with it...
- uvc gadget driver updates as more devices start to use and
rely on this hardware as well
- usb_maxpacket() api changes to remove an unneeded and unused
parameter.
- usb-serial driver device id updates and small cleanups
- typec cleanups and fixes based on device testing
- device tree updates for usb properties
- lots of other small fixes and driver updates.
All of these have been in linux-next for weeks with no reported
problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'usb-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB / Thunderbolt updates from Greg KH:
"Here is the "big" set of USB and Thunderbolt driver changes for
5.18-rc1. For the most part it's been a quiet development cycle for
the USB core, but there are the usual "hot spots" of development
activity.
Included in here are:
- Thunderbolt driver updates:
- fixes for devices without displayport adapters
- lane bonding support and improvements
- other minor changes based on device testing
- dwc3 gadget driver changes.
It seems this driver will never be finished given that the IP core
is showing up in zillions of new devices and each implementation
decides to do something different with it...
- uvc gadget driver updates as more devices start to use and rely on
this hardware as well
- usb_maxpacket() api changes to remove an unneeded and unused
parameter.
- usb-serial driver device id updates and small cleanups
- typec cleanups and fixes based on device testing
- device tree updates for usb properties
- lots of other small fixes and driver updates.
All of these have been in linux-next for weeks with no reported
problems"
* tag 'usb-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (154 commits)
USB: new quirk for Dell Gen 2 devices
usb: dwc3: core: Add error log when core soft reset failed
usb: dwc3: gadget: Move null pinter check to proper place
usb: hub: Simplify error and success path in port_over_current_notify
usb: cdns3: allocate TX FIFO size according to composite EP number
usb: dwc3: Fix ep0 handling when getting reset while doing control transfer
usb: Probe EHCI, OHCI controllers asynchronously
usb: isp1760: Fix out-of-bounds array access
xhci: Don't defer primary roothub registration if there is only one roothub
USB: serial: option: add Quectel BG95 modem
USB: serial: pl2303: fix type detection for odd device
xhci: Allow host runtime PM as default for Intel Alder Lake N xHCI
xhci: Remove quirk for over 10 year old evaluation hardware
xhci: prevent U2 link power state if Intel tier policy prevented U1
xhci: use generic command timer for stop endpoint commands.
usb: host: xhci-plat: omit shared hcd if either root hub has no ports
usb: host: xhci-plat: prepare operation w/o shared hcd
usb: host: xhci-plat: create shared hcd after having added main hcd
xhci: prepare for operation w/o shared hcd
xhci: factor out parts of xhci_gen_setup()
...
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1108 lines
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8994.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8994.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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mmc1 = &sdhc1;
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mmc2 = &sdhc2;
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};
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "sleep_clk";
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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};
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CPU6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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};
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CPU7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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cpu6_map: core2 {
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cpu = <&CPU6>;
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};
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cpu7_map: core3 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8994", "qcom,scm";
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0x80000000 0 0>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x80>;
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#hwlock-cells = <1>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "hvc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dfps_data_mem: dfps_data_mem@3400000 {
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reg = <0 0x03400000 0 0x1000>;
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no-map;
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};
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cont_splash_mem: memory@3401000 {
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reg = <0 0x03401000 0 0x2200000>;
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no-map;
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};
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smem_mem: smem_region@6a00000 {
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reg = <0 0x06a00000 0 0x200000>;
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no-map;
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};
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mpss_mem: memory@7000000 {
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reg = <0 0x07000000 0 0x5a00000>;
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no-map;
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};
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peripheral_region: memory@ca00000 {
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reg = <0 0x0ca00000 0 0x1f00000>;
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no-map;
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};
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rmtfs_mem: memory@c6400000 {
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compatible = "qcom,rmtfs-mem";
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reg = <0 0xc6400000 0 0x180000>;
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no-map;
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qcom,client-id = <1>;
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};
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mba_mem: memory@c6700000 {
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reg = <0 0xc6700000 0 0x100000>;
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no-map;
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};
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audio_mem: memory@c7000000 {
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reg = <0 0xc7000000 0 0x800000>;
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no-map;
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};
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adsp_mem: memory@c9400000 {
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reg = <0 0xc9400000 0 0x3f00000>;
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no-map;
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};
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};
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smd {
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compatible = "qcom,smd";
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rpm {
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 0>;
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qcom,smd-edge = <15>;
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qcom,remote-pid = <6>;
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-msm8994";
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qcom,smd-channels = "rpm_requests";
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rpmcc: rpmcc {
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compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
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#clock-cells = <1>;
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};
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rpmpd: power-controller {
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compatible = "qcom,msm8994-rpmpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmpd_opp_table>;
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rpmpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmpd_opp_ret: opp1 {
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opp-level = <1>;
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};
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rpmpd_opp_svs_krait: opp2 {
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opp-level = <2>;
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};
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rpmpd_opp_svs_soc: opp3 {
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opp-level = <3>;
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};
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rpmpd_opp_nom: opp4 {
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opp-level = <4>;
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};
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rpmpd_opp_turbo: opp5 {
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opp-level = <5>;
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};
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rpmpd_opp_super_turbo: opp6 {
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opp-level = <6>;
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};
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};
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};
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};
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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hwlocks = <&tcsr_mutex 3>;
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};
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smp2p-lpass {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 10>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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adsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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smp2p-modem {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
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qcom,ipc = <&apcs 8 14>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0xf9000000 0x1000>,
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<0xf9002000 0x1000>;
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};
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apcs: mailbox@f900d000 {
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compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
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reg = <0xf900d000 0x2000>;
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#mbox-cells = <1>;
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};
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watchdog@f9017000 {
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compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
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reg = <0xf9017000 0x1000>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
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clocks = <&sleep_clk>;
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timeout-sec = <10>;
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};
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timer@f9020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf9020000 0x1000>;
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frame@f9021000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9021000 0x1000>,
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<0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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};
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frame@f9028000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf9028000 0x1000>;
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status = "disabled";
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};
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};
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usb3: usb@f92f8800 {
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compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
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reg = <0xf92f8800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>;
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clock-names = "core",
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"iface",
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"sleep",
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"mock_utmi";
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assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <120000000>;
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power-domains = <&gcc USB30_GDSC>;
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qcom,select-utmi-as-pipe-clk;
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usb@f9200000 {
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compatible = "snps,dwc3";
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reg = <0xf9200000 0xcc00>;
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interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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maximum-speed = "high-speed";
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dr_mode = "peripheral";
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};
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};
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sdhc1: sdhci@f9824900 {
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compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&xo_board>;
|
|
clock-names = "core", "iface", "xo";
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
|
|
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
|
|
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhc2: sdhci@f98a4900 {
|
|
compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
|
|
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
|
|
reg-names = "hc_mem", "core_mem";
|
|
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
|
|
<&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&xo_board>;
|
|
clock-names = "core", "iface", "xo";
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
|
|
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
|
|
|
|
cd-gpios = <&tlmm 100 0>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_dma: dma-controller@f9904000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0xf9904000 0x19000>;
|
|
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
qcom,controlled-remotely;
|
|
num-channels = <24>;
|
|
qcom,num-ees = <4>;
|
|
};
|
|
|
|
blsp1_uart2: serial@f991e000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0xf991e000 0x1000>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "iface";
|
|
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&blsp1_uart2_default>;
|
|
pinctrl-1 = <&blsp1_uart2_sleep>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c1: i2c@f9923000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xf9923000 0x500>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c1_default>;
|
|
pinctrl-1 = <&i2c1_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_spi1: spi@f9923000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0xf9923000 0x500>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
spi-max-frequency = <19200000>;
|
|
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&blsp1_spi1_default>;
|
|
pinctrl-1 = <&blsp1_spi1_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c2: i2c@f9924000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xf9924000 0x500>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c2_default>;
|
|
pinctrl-1 = <&i2c2_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C3 doesn't exist */
|
|
|
|
blsp1_i2c4: i2c@f9926000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xf9926000 0x500>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c4_default>;
|
|
pinctrl-1 = <&i2c4_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c5: i2c@f9927000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xf9927000 0x500>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c5_default>;
|
|
pinctrl-1 = <&i2c5_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp1_i2c6: i2c@f9928000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xf9928000 0x500>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c6_default>;
|
|
pinctrl-1 = <&i2c6_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_dma: dma-controller@f9944000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0xf9944000 0x19000>;
|
|
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "bam_clk";
|
|
#dma-cells = <1>;
|
|
qcom,ee = <0>;
|
|
qcom,controlled-remotely;
|
|
num-channels = <24>;
|
|
qcom,num-ees = <4>;
|
|
};
|
|
|
|
blsp2_uart2: serial@f995e000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0xf995e000 0x1000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "core", "iface";
|
|
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&blsp2_uart2_default>;
|
|
pinctrl-1 = <&blsp2_uart2_sleep>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_i2c1: i2c@f9963000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xf9963000 0x500>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <400000>;
|
|
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c7_default>;
|
|
pinctrl-1 = <&i2c7_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_spi4: spi@f9966000 {
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0xf9966000 0x500>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
spi-max-frequency = <19200000>;
|
|
dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&blsp2_spi10_default>;
|
|
pinctrl-1 = <&blsp2_spi10_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_i2c5: i2c@f9967000 {
|
|
compatible = "qcom,i2c-qup-v2.2.1";
|
|
reg = <0xf9967000 0x500>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <355000>;
|
|
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&i2c11_default>;
|
|
pinctrl-1 = <&i2c11_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gcc: clock-controller@fc400000 {
|
|
compatible = "qcom,gcc-msm8994";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
reg = <0xfc400000 0x2000>;
|
|
|
|
clock-names = "xo", "sleep";
|
|
clocks = <&xo_board>, <&sleep_clk>;
|
|
};
|
|
|
|
rpm_msg_ram: sram@fc428000 {
|
|
compatible = "qcom,rpm-msg-ram";
|
|
reg = <0xfc428000 0x4000>;
|
|
};
|
|
|
|
restart@fc4ab000 {
|
|
compatible = "qcom,pshold";
|
|
reg = <0xfc4ab000 0x4>;
|
|
};
|
|
|
|
spmi_bus: spmi@fc4c0000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xfc4cf000 0x1000>,
|
|
<0xfc4cb000 0x1000>,
|
|
<0xfc4ca000 0x1000>;
|
|
reg-names = "core", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|
|
tcsr_mutex_regs: syscon@fd484000 {
|
|
compatible = "syscon";
|
|
reg = <0xfd484000 0x2000>;
|
|
};
|
|
|
|
tlmm: pinctrl@fd510000 {
|
|
compatible = "qcom,msm8994-pinctrl";
|
|
reg = <0xfd510000 0x4000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
gpio-ranges = <&tlmm 0 0 146>;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
blsp1_uart2_default: blsp1-uart2-default {
|
|
function = "blsp_uart2";
|
|
pins = "gpio4", "gpio5";
|
|
drive-strength = <16>;
|
|
bias-disable;
|
|
};
|
|
|
|
blsp1_uart2_sleep: blsp1-uart2-sleep {
|
|
function = "gpio";
|
|
pins = "gpio4", "gpio5";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
blsp2_uart2_default: blsp2-uart2-default {
|
|
function = "blsp_uart8";
|
|
pins = "gpio45", "gpio46",
|
|
"gpio47", "gpio48";
|
|
drive-strength = <16>;
|
|
bias-disable;
|
|
};
|
|
|
|
blsp2_uart2_sleep: blsp2-uart2-sleep {
|
|
function = "gpio";
|
|
pins = "gpio45", "gpio46",
|
|
"gpio47", "gpio48";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c1_default: i2c1-default {
|
|
function = "blsp_i2c1";
|
|
pins = "gpio2", "gpio3";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c1_sleep: i2c1-sleep {
|
|
function = "gpio";
|
|
pins = "gpio2", "gpio3";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c2_default: i2c2-default {
|
|
function = "blsp_i2c2";
|
|
pins = "gpio6", "gpio7";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c2_sleep: i2c2-sleep {
|
|
function = "gpio";
|
|
pins = "gpio6", "gpio7";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c4_default: i2c4-default {
|
|
function = "blsp_i2c4";
|
|
pins = "gpio19", "gpio20";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c4_sleep: i2c4-sleep {
|
|
function = "gpio";
|
|
pins = "gpio19", "gpio20";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
|
|
i2c5_default: i2c5-default {
|
|
function = "blsp_i2c5";
|
|
pins = "gpio23", "gpio24";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c5_sleep: i2c5-sleep {
|
|
function = "gpio";
|
|
pins = "gpio23", "gpio24";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c6_default: i2c6-default {
|
|
function = "blsp_i2c6";
|
|
pins = "gpio28", "gpio27";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c6_sleep: i2c6-sleep {
|
|
function = "gpio";
|
|
pins = "gpio28", "gpio27";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c7_default: i2c7-default {
|
|
function = "blsp_i2c7";
|
|
pins = "gpio44", "gpio43";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c7_sleep: i2c7-sleep {
|
|
function = "gpio";
|
|
pins = "gpio44", "gpio43";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
blsp2_spi10_default: blsp2-spi10-default {
|
|
default {
|
|
function = "blsp_spi10";
|
|
pins = "gpio53", "gpio54", "gpio55";
|
|
drive-strength = <10>;
|
|
bias-pull-down;
|
|
};
|
|
cs {
|
|
function = "gpio";
|
|
pins = "gpio55";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp2_spi10_sleep: blsp2-spi10-sleep {
|
|
pins = "gpio53", "gpio54", "gpio55";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c11_default: i2c11-default {
|
|
function = "blsp_i2c11";
|
|
pins = "gpio83", "gpio84";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
i2c11_sleep: i2c11-sleep {
|
|
function = "gpio";
|
|
pins = "gpio83", "gpio84";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
blsp1_spi1_default: blsp1-spi1-default {
|
|
default {
|
|
function = "blsp_spi1";
|
|
pins = "gpio0", "gpio1", "gpio3";
|
|
drive-strength = <10>;
|
|
bias-pull-down;
|
|
};
|
|
cs {
|
|
function = "gpio";
|
|
pins = "gpio8";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
blsp1_spi1_sleep: blsp1-spi1-sleep {
|
|
pins = "gpio0", "gpio1", "gpio3";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
sdc1_clk_on: clk-on {
|
|
pins = "sdc1_clk";
|
|
bias-disable;
|
|
drive-strength = <16>;
|
|
};
|
|
|
|
sdc1_clk_off: clk-off {
|
|
pins = "sdc1_clk";
|
|
bias-disable;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
sdc1_cmd_on: cmd-on {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
sdc1_cmd_off: cmd-off {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
sdc1_data_on: data-on {
|
|
pins = "sdc1_data";
|
|
bias-pull-up;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
sdc1_data_off: data-off {
|
|
pins = "sdc1_data";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
sdc1_rclk_on: rclk-on {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down;
|
|
};
|
|
|
|
sdc1_rclk_off: rclk-off {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down;
|
|
};
|
|
|
|
sdc2_clk_on: sdc2-clk-on {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
sdc2_clk_off: sdc2-clk-off {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
sdc2_cmd_on: sdc2-cmd-on {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
sdc2_cmd_off: sdc2-cmd-off {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
sdc2_data_on: sdc2-data-on {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
sdc2_data_off: sdc2-data-off {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
|
|
mmcc: clock-controller@fd8c0000 {
|
|
compatible = "qcom,mmcc-msm8994";
|
|
reg = <0xfd8c0000 0x5200>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
|
|
clock-names = "xo",
|
|
"gpll0",
|
|
"mmssnoc_ahb",
|
|
"oxili_gfx3d_clk_src",
|
|
"dsi0pll",
|
|
"dsi0pllbyte",
|
|
"dsi1pll",
|
|
"dsi1pllbyte",
|
|
"hdmipll";
|
|
clocks = <&xo_board>,
|
|
<&gcc GPLL0_OUT_MMSSCC>,
|
|
<&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
|
|
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>;
|
|
|
|
assigned-clocks = <&mmcc MMPLL0_PLL>,
|
|
<&mmcc MMPLL1_PLL>,
|
|
<&mmcc MMPLL3_PLL>,
|
|
<&mmcc MMPLL4_PLL>,
|
|
<&mmcc MMPLL5_PLL>;
|
|
assigned-clock-rates = <800000000>,
|
|
<1167000000>,
|
|
<1020000000>,
|
|
<960000000>,
|
|
<600000000>;
|
|
};
|
|
|
|
ocmem: ocmem@fdd00000 {
|
|
compatible = "qcom,msm8974-ocmem";
|
|
reg = <0xfdd00000 0x2000>,
|
|
<0xfec00000 0x200000>;
|
|
reg-names = "ctrl", "mem";
|
|
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
|
|
<&mmcc OCMEMCX_OCMEMNOC_CLK>;
|
|
clock-names = "core", "iface";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
gmu_sram: gmu-sram@0 {
|
|
reg = <0x0 0x180000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 2 0xff08>,
|
|
<GIC_PPI 3 0xff08>,
|
|
<GIC_PPI 4 0xff08>,
|
|
<GIC_PPI 1 0xff08>;
|
|
};
|
|
|
|
vph_pwr: vph-pwr-regulator {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vph_pwr";
|
|
|
|
regulator-min-microvolt = <3600000>;
|
|
regulator-max-microvolt = <3600000>;
|
|
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
|