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e20ef23dd6
We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Cc: devicetree@vger.kernel.org Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Rob Herring <robh@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
297 lines
7.3 KiB
C
297 lines
7.3 KiB
C
/*
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* omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
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*
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* Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is automatically generated from the AM33XX hardware databases.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "omap_hwmod.h"
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#include "omap_hwmod_common_data.h"
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#include "control.h"
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#include "cm33xx.h"
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#include "prm33xx.h"
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#include "prm-regbits-33xx.h"
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#include "omap_hwmod_33xx_43xx_common_data.h"
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/*
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* IP blocks
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*/
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/* emif */
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static struct omap_hwmod am33xx_emif_hwmod = {
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.name = "emif",
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.class = &am33xx_emif_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_ddr_m2_div2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* l4_hs */
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static struct omap_hwmod am33xx_l4_hs_hwmod = {
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.name = "l4_hs",
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.class = &am33xx_l4_hwmod_class,
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.clkdm_name = "l4hs_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l4hs_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
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{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
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};
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/* wkup_m3 */
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static struct omap_hwmod am33xx_wkup_m3_hwmod = {
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.name = "wkup_m3",
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.class = &am33xx_wkup_m3_hwmod_class,
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.clkdm_name = "l4_wkup_aon_clkdm",
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/* Keep hardreset asserted */
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.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
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.main_clk = "dpll_core_m4_div2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
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.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
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.rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.rst_lines = am33xx_wkup_m3_resets,
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.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
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};
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/*
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* Modules omap_hwmod structures
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*
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* The following IPs are excluded for the moment because:
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* - They do not need an explicit SW control using omap_hwmod API.
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* - They still need to be validated with the driver
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* properly adapted to omap_hwmod / omap_device
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*
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* - cEFUSE (doesn't fall under any ocp_if)
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* - clkdiv32k
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* - ocp watch point
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*/
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#if 0
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/*
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* 'cefuse' class
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*/
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static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
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.name = "cefuse",
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};
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static struct omap_hwmod am33xx_cefuse_hwmod = {
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.name = "cefuse",
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.class = &am33xx_cefuse_hwmod_class,
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.clkdm_name = "l4_cefuse_clkdm",
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.main_clk = "cefuse_fck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'clkdiv32k' class
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*/
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static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
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.name = "clkdiv32k",
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};
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static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
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.name = "clkdiv32k",
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.class = &am33xx_clkdiv32k_hwmod_class,
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.clkdm_name = "clk_24mhz_clkdm",
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.main_clk = "clkdiv32k_ick",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* ocpwp */
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static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
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.name = "ocpwp",
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};
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static struct omap_hwmod am33xx_ocpwp_hwmod = {
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.name = "ocpwp",
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.class = &am33xx_ocpwp_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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#endif
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/*
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* 'debugss' class
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* debug sub system
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*/
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static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
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{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
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{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
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};
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static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
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.name = "debugss",
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};
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static struct omap_hwmod am33xx_debugss_hwmod = {
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.name = "debugss",
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.class = &am33xx_debugss_hwmod_class,
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.clkdm_name = "l3_aon_clkdm",
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.main_clk = "trace_clk_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = debugss_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
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};
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static struct omap_hwmod am33xx_control_hwmod = {
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.name = "control",
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.class = &am33xx_control_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_core_m4_div2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* Interfaces
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*/
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/* l3 main -> emif */
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static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
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.master = &am33xx_l3_main_hwmod,
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.slave = &am33xx_emif_hwmod,
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.clk = "dpll_core_m4_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3 main -> l4 hs */
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static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
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.master = &am33xx_l3_main_hwmod,
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.slave = &am33xx_l4_hs_hwmod,
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.clk = "l3s_gclk",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* wkup m3 -> l4 wkup */
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static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
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.master = &am33xx_wkup_m3_hwmod,
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.slave = &am33xx_l4_wkup_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4 wkup -> wkup m3 */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_wkup_m3_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main -> debugss */
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static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
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.master = &am33xx_l3_main_hwmod,
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.slave = &am33xx_debugss_hwmod,
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.clk = "dpll_core_m4_ck",
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.user = OCP_USER_MPU,
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};
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/* l4 wkup -> smartreflex0 */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_smartreflex0_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU,
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};
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/* l4 wkup -> smartreflex1 */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_smartreflex1_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU,
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};
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/* l4 wkup -> control */
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static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
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.master = &am33xx_l4_wkup_hwmod,
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.slave = &am33xx_control_hwmod,
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.clk = "dpll_core_m4_div2_ck",
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.user = OCP_USER_MPU,
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};
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static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
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&am33xx_l3_main__emif,
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&am33xx_mpu__l3_main,
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&am33xx_mpu__prcm,
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&am33xx_l3_s__l4_ls,
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&am33xx_l3_s__l4_wkup,
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&am33xx_l3_main__l4_hs,
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&am33xx_l3_main__l3_s,
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&am33xx_l3_main__l3_instr,
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&am33xx_l3_main__gfx,
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&am33xx_l3_s__l3_main,
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&am33xx_wkup_m3__l4_wkup,
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&am33xx_gfx__l3_main,
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&am33xx_l3_main__debugss,
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&am33xx_l4_wkup__wkup_m3,
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&am33xx_l4_wkup__control,
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&am33xx_l4_wkup__smartreflex0,
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&am33xx_l4_wkup__smartreflex1,
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&am33xx_l4_wkup__rtc,
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&am33xx_l3_s__gpmc,
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&am33xx_l3_main__ocmc,
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NULL,
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};
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int __init am33xx_hwmod_init(void)
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{
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omap_hwmod_am33xx_reg();
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omap_hwmod_init();
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return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
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}
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