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e5fab2ec9c
This patch adds clocking support for the YUV420 output from the Amlogic Meson SoCs Video Processing Unit to the HDMI Controller. The YUV420 is obtained by generating a YUV444 pixel stream like the classic HDMI display modes, but then the Video Encoder output can be configured to down-sample the YUV444 pixel stream to a YUV420 stream. This mode needs a different clock generation scheme since the TMDS PHY clock must match the 10x ratio with the YUV420 pixel clock, but the video encoder must run at 2x the pixel clock. This patch adds the TMDS PHY clock value in all the video clock setup in order to better support these specific uses cases and switch to the Common Clock framework for clocks handling in the future. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jernej Škrabec <jernej.skrabec@siol.net> Link: https://patchwork.freedesktop.org/patch/msgid/20200304104052.17196-11-narmstrong@baylibre.com
35 lines
853 B
C
35 lines
853 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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/* Video Clock */
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#ifndef __MESON_VCLK_H
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#define __MESON_VCLK_H
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#include <drm/drm_modes.h>
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struct meson_drm;
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enum {
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MESON_VCLK_TARGET_CVBS = 0,
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MESON_VCLK_TARGET_HDMI = 1,
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MESON_VCLK_TARGET_DMT = 2,
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};
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/* 27MHz is the CVBS Pixel Clock */
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#define MESON_VCLK_CVBS 27000
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enum drm_mode_status
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meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
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enum drm_mode_status
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meson_vclk_vic_supported_freq(unsigned int phy_freq, unsigned int vclk_freq);
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void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
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unsigned int phy_freq, unsigned int vclk_freq,
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unsigned int venc_freq, unsigned int dac_freq,
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bool hdmi_use_enci);
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#endif /* __MESON_VCLK_H */
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