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![Yoshihiro Shimoda](/assets/img/avatar_default.png)
The previous code had hardcoded the PHY_INTERFACE_MODE_MII of phy_connect. So some Gigabit PHYs will not behave correctly. The patch adds the phy_interface in sh_eth_plat_data, so we can select the phy interface. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
837 lines
18 KiB
C
837 lines
18 KiB
C
/*
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* SuperH Ethernet device driver
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*
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* Copyright (C) 2006-2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008-2011 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*/
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#ifndef __SH_ETH_H__
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#define __SH_ETH_H__
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <asm/sh_eth.h>
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#define CARDNAME "sh-eth"
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#define TX_TIMEOUT (5*HZ)
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#define TX_RING_SIZE 64 /* Tx ring size */
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#define RX_RING_SIZE 64 /* Rx ring size */
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#define ETHERSMALL 60
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#define PKT_BUF_SZ 1538
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enum {
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/* E-DMAC registers */
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EDSR = 0,
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EDMR,
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EDTRR,
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EDRRR,
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EESR,
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EESIPR,
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TDLAR,
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TDFAR,
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TDFXR,
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TDFFR,
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RDLAR,
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RDFAR,
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RDFXR,
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RDFFR,
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TRSCER,
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RMFCR,
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TFTR,
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FDR,
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RMCR,
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EDOCR,
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TFUCR,
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RFOCR,
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FCFTR,
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RPADIR,
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TRIMD,
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RBWAR,
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TBRAR,
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/* Ether registers */
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ECMR,
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ECSR,
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ECSIPR,
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PIR,
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PSR,
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RDMLR,
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PIPR,
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RFLR,
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IPGR,
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APR,
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MPR,
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PFTCR,
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PFRCR,
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RFCR,
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RFCF,
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TPAUSER,
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TPAUSECR,
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BCFR,
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BCFRR,
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GECMR,
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BCULR,
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MAHR,
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MALR,
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TROCR,
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CDCR,
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LCCR,
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CNDCR,
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CEFCR,
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FRECR,
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TSFRCR,
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TLFRCR,
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CERCR,
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CEECR,
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MAFCR,
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RTRATE,
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/* TSU Absolute address */
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ARSTR,
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TSU_CTRST,
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TSU_FWEN0,
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TSU_FWEN1,
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TSU_FCM,
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TSU_BSYSL0,
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TSU_BSYSL1,
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TSU_PRISL0,
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TSU_PRISL1,
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TSU_FWSL0,
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TSU_FWSL1,
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TSU_FWSLC,
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TSU_QTAG0,
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TSU_QTAG1,
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TSU_QTAGM0,
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TSU_QTAGM1,
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TSU_FWSR,
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TSU_FWINMK,
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TSU_ADQT0,
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TSU_ADQT1,
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TSU_VTAG0,
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TSU_VTAG1,
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TSU_ADSBSY,
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TSU_TEN,
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TSU_POST1,
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TSU_POST2,
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TSU_POST3,
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TSU_POST4,
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TSU_ADRH0,
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TSU_ADRL0,
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TSU_ADRH31,
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TSU_ADRL31,
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TXNLCR0,
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TXALCR0,
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RXNLCR0,
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RXALCR0,
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FWNLCR0,
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FWALCR0,
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TXNLCR1,
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TXALCR1,
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RXNLCR1,
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RXALCR1,
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FWNLCR1,
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FWALCR1,
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/* This value must be written at last. */
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SH_ETH_MAX_REGISTER_OFFSET,
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};
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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[EDSR] = 0x0000,
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[EDMR] = 0x0400,
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[EDTRR] = 0x0408,
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[EDRRR] = 0x0410,
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[EESR] = 0x0428,
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[EESIPR] = 0x0430,
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[TDLAR] = 0x0010,
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[TDFAR] = 0x0014,
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[TDFXR] = 0x0018,
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[TDFFR] = 0x001c,
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[RDLAR] = 0x0030,
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[RDFAR] = 0x0034,
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[RDFXR] = 0x0038,
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[RDFFR] = 0x003c,
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[TRSCER] = 0x0438,
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[RMFCR] = 0x0440,
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[TFTR] = 0x0448,
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[FDR] = 0x0450,
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[RMCR] = 0x0458,
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[RPADIR] = 0x0460,
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[FCFTR] = 0x0468,
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[ECMR] = 0x0500,
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[ECSR] = 0x0510,
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[ECSIPR] = 0x0518,
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[PIR] = 0x0520,
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[PSR] = 0x0528,
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[PIPR] = 0x052c,
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[RFLR] = 0x0508,
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[APR] = 0x0554,
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[MPR] = 0x0558,
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[PFTCR] = 0x055c,
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[PFRCR] = 0x0560,
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[TPAUSER] = 0x0564,
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[GECMR] = 0x05b0,
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[BCULR] = 0x05b4,
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[MAHR] = 0x05c0,
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[MALR] = 0x05c8,
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[TROCR] = 0x0700,
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[CDCR] = 0x0708,
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[LCCR] = 0x0710,
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[CEFCR] = 0x0740,
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[FRECR] = 0x0748,
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[TSFRCR] = 0x0750,
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[TLFRCR] = 0x0758,
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[RFCR] = 0x0760,
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[CERCR] = 0x0768,
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[CEECR] = 0x0770,
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[MAFCR] = 0x0778,
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[ARSTR] = 0x0000,
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[TSU_CTRST] = 0x0004,
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[TSU_FWEN0] = 0x0010,
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[TSU_FWEN1] = 0x0014,
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[TSU_FCM] = 0x0018,
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[TSU_BSYSL0] = 0x0020,
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[TSU_BSYSL1] = 0x0024,
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[TSU_PRISL0] = 0x0028,
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[TSU_PRISL1] = 0x002c,
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[TSU_FWSL0] = 0x0030,
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[TSU_FWSL1] = 0x0034,
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[TSU_FWSLC] = 0x0038,
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[TSU_QTAG0] = 0x0040,
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[TSU_QTAG1] = 0x0044,
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[TSU_FWSR] = 0x0050,
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[TSU_FWINMK] = 0x0054,
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[TSU_ADQT0] = 0x0048,
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[TSU_ADQT1] = 0x004c,
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[TSU_VTAG0] = 0x0058,
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[TSU_VTAG1] = 0x005c,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TSU_ADRH0] = 0x0100,
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[TSU_ADRL0] = 0x0104,
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[TSU_ADRH31] = 0x01f8,
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[TSU_ADRL31] = 0x01fc,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008c,
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[FWNLCR0] = 0x0090,
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[FWALCR0] = 0x0094,
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[TXNLCR1] = 0x00a0,
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[TXALCR1] = 0x00a0,
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[RXNLCR1] = 0x00a8,
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[RXALCR1] = 0x00ac,
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[FWNLCR1] = 0x00b0,
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[FWALCR1] = 0x00b4,
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};
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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0100,
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[RFLR] = 0x0108,
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[ECSR] = 0x0110,
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[ECSIPR] = 0x0118,
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[PIR] = 0x0120,
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[PSR] = 0x0128,
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[RDMLR] = 0x0140,
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[IPGR] = 0x0150,
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[APR] = 0x0154,
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[MPR] = 0x0158,
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[TPAUSER] = 0x0164,
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[RFCF] = 0x0160,
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[TPAUSECR] = 0x0168,
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[BCFRR] = 0x016c,
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[MAHR] = 0x01c0,
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[MALR] = 0x01c8,
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[TROCR] = 0x01d0,
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[CDCR] = 0x01d4,
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[LCCR] = 0x01d8,
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[CNDCR] = 0x01dc,
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[CEFCR] = 0x01e4,
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[FRECR] = 0x01e8,
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[TSFRCR] = 0x01ec,
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[TLFRCR] = 0x01f0,
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[RFCR] = 0x01f4,
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[MAFCR] = 0x01f8,
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[RTRATE] = 0x01fc,
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[EDMR] = 0x0000,
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[EDTRR] = 0x0008,
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[EDRRR] = 0x0010,
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[TDLAR] = 0x0018,
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[RDLAR] = 0x0020,
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[EESR] = 0x0028,
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[EESIPR] = 0x0030,
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[TRSCER] = 0x0038,
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[RMFCR] = 0x0040,
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[TFTR] = 0x0048,
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[FDR] = 0x0050,
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[RMCR] = 0x0058,
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[TFUCR] = 0x0064,
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[RFOCR] = 0x0068,
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[FCFTR] = 0x0070,
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[RPADIR] = 0x0078,
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[TRIMD] = 0x007c,
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[RBWAR] = 0x00c8,
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[RDFAR] = 0x00cc,
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[TBRAR] = 0x00d4,
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[TDFAR] = 0x00d8,
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};
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static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0160,
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[ECSR] = 0x0164,
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[ECSIPR] = 0x0168,
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[PIR] = 0x016c,
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[MAHR] = 0x0170,
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[MALR] = 0x0174,
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[RFLR] = 0x0178,
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[PSR] = 0x017c,
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[TROCR] = 0x0180,
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[CDCR] = 0x0184,
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[LCCR] = 0x0188,
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[CNDCR] = 0x018c,
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[CEFCR] = 0x0194,
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[FRECR] = 0x0198,
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[TSFRCR] = 0x019c,
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[TLFRCR] = 0x01a0,
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[RFCR] = 0x01a4,
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[MAFCR] = 0x01a8,
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[IPGR] = 0x01b4,
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[APR] = 0x01b8,
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[MPR] = 0x01bc,
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[TPAUSER] = 0x01c4,
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[BCFR] = 0x01cc,
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[ARSTR] = 0x0000,
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[TSU_CTRST] = 0x0004,
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[TSU_FWEN0] = 0x0010,
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[TSU_FWEN1] = 0x0014,
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[TSU_FCM] = 0x0018,
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[TSU_BSYSL0] = 0x0020,
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[TSU_BSYSL1] = 0x0024,
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[TSU_PRISL0] = 0x0028,
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[TSU_PRISL1] = 0x002c,
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[TSU_FWSL0] = 0x0030,
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[TSU_FWSL1] = 0x0034,
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[TSU_FWSLC] = 0x0038,
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[TSU_QTAGM0] = 0x0040,
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[TSU_QTAGM1] = 0x0044,
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[TSU_ADQT0] = 0x0048,
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[TSU_ADQT1] = 0x004c,
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[TSU_FWSR] = 0x0050,
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[TSU_FWINMK] = 0x0054,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008c,
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[FWNLCR0] = 0x0090,
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[FWALCR0] = 0x0094,
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[TXNLCR1] = 0x00a0,
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[TXALCR1] = 0x00a0,
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[RXNLCR1] = 0x00a8,
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[RXALCR1] = 0x00ac,
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[FWNLCR1] = 0x00b0,
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[FWALCR1] = 0x00b4,
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[TSU_ADRH0] = 0x0100,
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[TSU_ADRL0] = 0x0104,
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[TSU_ADRL31] = 0x01fc,
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};
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/* Driver's parameters */
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#if defined(CONFIG_CPU_SH4)
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#define SH4_SKB_RX_ALIGN 32
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#else
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#define SH2_SH3_SKB_RX_ALIGN 2
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#endif
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/*
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* Register's bits
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*/
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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/* EDSR */
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enum EDSR_BIT {
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EDSR_ENT = 0x01, EDSR_ENR = 0x02,
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};
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#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
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/* GECMR */
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enum GECMR_BIT {
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GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
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};
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#endif
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/* EDMR */
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enum DMAC_M_BIT {
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EDMR_EL = 0x40, /* Litte endian */
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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EDMR_SRST_GETHER = 0x03,
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EDMR_SRST_ETHER = 0x01,
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};
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/* EDTRR */
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enum DMAC_T_BIT {
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EDTRR_TRNS_GETHER = 0x03,
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EDTRR_TRNS_ETHER = 0x01,
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};
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/* EDRRR*/
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enum EDRRR_R_BIT {
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EDRRR_R = 0x01,
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};
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/* TPAUSER */
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enum TPAUSER_BIT {
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TPAUSER_TPAUSE = 0x0000ffff,
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TPAUSER_UNLIMITED = 0,
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};
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/* BCFR */
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enum BCFR_BIT {
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BCFR_RPAUSE = 0x0000ffff,
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BCFR_UNLIMITED = 0,
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};
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/* PIR */
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enum PIR_BIT {
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PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
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};
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/* PSR */
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enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
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/* EESR */
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enum EESR_BIT {
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EESR_TWB1 = 0x80000000,
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EESR_TWB = 0x40000000, /* same as TWB0 */
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EESR_TC1 = 0x20000000,
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EESR_TUC = 0x10000000,
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EESR_ROC = 0x08000000,
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EESR_TABT = 0x04000000,
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EESR_RABT = 0x02000000,
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EESR_RFRMER = 0x01000000, /* same as RFCOF */
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EESR_ADE = 0x00800000,
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EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, /* same as TC or TC0 */
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EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, /* same as TFUF */
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EESR_FRC = 0x00040000, /* same as FR */
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EESR_RDE = 0x00020000,
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EESR_RFE = 0x00010000,
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EESR_CND = 0x00000800,
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EESR_DLC = 0x00000400,
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EESR_CD = 0x00000200,
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EESR_RTO = 0x00000100,
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EESR_RMAF = 0x00000080,
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EESR_CEEF = 0x00000040,
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EESR_CELF = 0x00000020,
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EESR_RRF = 0x00000010,
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EESR_RTLF = 0x00000008,
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EESR_RTSF = 0x00000004,
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EESR_PRE = 0x00000002,
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EESR_CERF = 0x00000001,
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};
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#define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
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EESR_RTO)
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#define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \
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EESR_RDE | EESR_RFRMER | EESR_ADE | \
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EESR_TFE | EESR_TDE | EESR_ECI)
|
|
#define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
|
|
EESR_TFE)
|
|
|
|
/* EESIPR */
|
|
enum DMAC_IM_BIT {
|
|
DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
|
|
DMAC_M_RABT = 0x02000000,
|
|
DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
|
|
DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
|
|
DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
|
|
DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
|
|
DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
|
|
DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
|
|
DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
|
|
DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
|
|
DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
|
|
DMAC_M_RINT1 = 0x00000001,
|
|
};
|
|
|
|
/* Receive descriptor bit */
|
|
enum RD_STS_BIT {
|
|
RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
|
|
RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
|
|
RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
|
|
RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
|
|
RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
|
|
RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
|
|
RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
|
|
RD_RFS1 = 0x00000001,
|
|
};
|
|
#define RDF1ST RD_RFP1
|
|
#define RDFEND RD_RFP0
|
|
#define RD_RFP (RD_RFP1|RD_RFP0)
|
|
|
|
/* FCFTR */
|
|
enum FCFTR_BIT {
|
|
FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
|
|
FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
|
|
FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
|
|
};
|
|
#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
|
|
#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
|
|
|
|
/* Transfer descriptor bit */
|
|
enum TD_STS_BIT {
|
|
TD_TACT = 0x80000000,
|
|
TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
|
|
TD_TFP0 = 0x10000000,
|
|
};
|
|
#define TDF1ST TD_TFP1
|
|
#define TDFEND TD_TFP0
|
|
#define TD_TFP (TD_TFP1|TD_TFP0)
|
|
|
|
/* RMCR */
|
|
#define DEFAULT_RMCR_VALUE 0x00000000
|
|
|
|
/* ECMR */
|
|
enum FELIC_MODE_BIT {
|
|
ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
|
|
ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
|
|
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
|
|
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
|
|
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
|
|
ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
|
|
ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
|
|
};
|
|
|
|
/* ECSR */
|
|
enum ECSR_STATUS_BIT {
|
|
ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
|
|
ECSR_LCHNG = 0x04,
|
|
ECSR_MPD = 0x02, ECSR_ICD = 0x01,
|
|
};
|
|
|
|
#define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
|
|
ECSR_ICD | ECSIPR_MPDIP)
|
|
|
|
/* ECSIPR */
|
|
enum ECSIPR_STATUS_MASK_BIT {
|
|
ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
|
|
ECSIPR_LCHNGIP = 0x04,
|
|
ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
|
|
};
|
|
|
|
#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
|
|
ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
|
|
|
|
/* APR */
|
|
enum APR_BIT {
|
|
APR_AP = 0x00000001,
|
|
};
|
|
|
|
/* MPR */
|
|
enum MPR_BIT {
|
|
MPR_MP = 0x00000001,
|
|
};
|
|
|
|
/* TRSCER */
|
|
enum DESC_I_BIT {
|
|
DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
|
|
DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
|
|
DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
|
|
DESC_I_RINT1 = 0x0001,
|
|
};
|
|
|
|
/* RPADIR */
|
|
enum RPADIR_BIT {
|
|
RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
|
|
RPADIR_PADR = 0x0003f,
|
|
};
|
|
|
|
/* RFLR */
|
|
#define RFLR_VALUE 0x1000
|
|
|
|
/* FDR */
|
|
#define DEFAULT_FDR_INIT 0x00000707
|
|
|
|
enum phy_offsets {
|
|
PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
|
|
PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
|
|
PHY_16 = 16,
|
|
};
|
|
|
|
/* PHY_CTRL */
|
|
enum PHY_CTRL_BIT {
|
|
PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
|
|
PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
|
|
PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
|
|
};
|
|
#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
|
|
|
|
/* PHY_STAT */
|
|
enum PHY_STAT_BIT {
|
|
PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
|
|
PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
|
|
PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
|
|
PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
|
|
};
|
|
|
|
/* PHY_ANA */
|
|
enum PHY_ANA_BIT {
|
|
PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
|
|
PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
|
|
PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
|
|
PHY_A_SEL = 0x001e,
|
|
};
|
|
/* PHY_ANL */
|
|
enum PHY_ANL_BIT {
|
|
PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
|
|
PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
|
|
PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
|
|
PHY_L_SEL = 0x001f,
|
|
};
|
|
|
|
/* PHY_ANE */
|
|
enum PHY_ANE_BIT {
|
|
PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
|
|
PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
|
|
};
|
|
|
|
/* DM9161 */
|
|
enum PHY_16_BIT {
|
|
PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
|
|
PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
|
|
PHY_16_TXselect = 0x0400,
|
|
PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
|
|
PHY_16_Force100LNK = 0x0080,
|
|
PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
|
|
PHY_16_RPDCTR_EN = 0x0010,
|
|
PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
|
|
PHY_16_Sleepmode = 0x0002,
|
|
PHY_16_RemoteLoopOut = 0x0001,
|
|
};
|
|
|
|
#define POST_RX 0x08
|
|
#define POST_FW 0x04
|
|
#define POST0_RX (POST_RX)
|
|
#define POST0_FW (POST_FW)
|
|
#define POST1_RX (POST_RX >> 2)
|
|
#define POST1_FW (POST_FW >> 2)
|
|
#define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
|
|
|
|
/* ARSTR */
|
|
enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
|
|
|
|
/* TSU_FWEN0 */
|
|
enum TSU_FWEN0_BIT {
|
|
TSU_FWEN0_0 = 0x00000001,
|
|
};
|
|
|
|
/* TSU_ADSBSY */
|
|
enum TSU_ADSBSY_BIT {
|
|
TSU_ADSBSY_0 = 0x00000001,
|
|
};
|
|
|
|
/* TSU_TEN */
|
|
enum TSU_TEN_BIT {
|
|
TSU_TEN_0 = 0x80000000,
|
|
};
|
|
|
|
/* TSU_FWSL0 */
|
|
enum TSU_FWSL0_BIT {
|
|
TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
|
|
TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
|
|
TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
|
|
};
|
|
|
|
/* TSU_FWSLC */
|
|
enum TSU_FWSLC_BIT {
|
|
TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
|
|
TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
|
|
TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
|
|
TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
|
|
TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
|
|
};
|
|
|
|
/*
|
|
* The sh ether Tx buffer descriptors.
|
|
* This structure should be 20 bytes.
|
|
*/
|
|
struct sh_eth_txdesc {
|
|
u32 status; /* TD0 */
|
|
#if defined(CONFIG_CPU_LITTLE_ENDIAN)
|
|
u16 pad0; /* TD1 */
|
|
u16 buffer_length; /* TD1 */
|
|
#else
|
|
u16 buffer_length; /* TD1 */
|
|
u16 pad0; /* TD1 */
|
|
#endif
|
|
u32 addr; /* TD2 */
|
|
u32 pad1; /* padding data */
|
|
} __attribute__((aligned(2), packed));
|
|
|
|
/*
|
|
* The sh ether Rx buffer descriptors.
|
|
* This structure should be 20 bytes.
|
|
*/
|
|
struct sh_eth_rxdesc {
|
|
u32 status; /* RD0 */
|
|
#if defined(CONFIG_CPU_LITTLE_ENDIAN)
|
|
u16 frame_length; /* RD1 */
|
|
u16 buffer_length; /* RD1 */
|
|
#else
|
|
u16 buffer_length; /* RD1 */
|
|
u16 frame_length; /* RD1 */
|
|
#endif
|
|
u32 addr; /* RD2 */
|
|
u32 pad0; /* padding data */
|
|
} __attribute__((aligned(2), packed));
|
|
|
|
/* This structure is used by each CPU dependency handling. */
|
|
struct sh_eth_cpu_data {
|
|
/* optional functions */
|
|
void (*chip_reset)(struct net_device *ndev);
|
|
void (*set_duplex)(struct net_device *ndev);
|
|
void (*set_rate)(struct net_device *ndev);
|
|
|
|
/* mandatory initialize value */
|
|
unsigned long eesipr_value;
|
|
|
|
/* optional initialize value */
|
|
unsigned long ecsr_value;
|
|
unsigned long ecsipr_value;
|
|
unsigned long fdr_value;
|
|
unsigned long fcftr_value;
|
|
unsigned long rpadir_value;
|
|
unsigned long rmcr_value;
|
|
|
|
/* interrupt checking mask */
|
|
unsigned long tx_check;
|
|
unsigned long eesr_err_check;
|
|
unsigned long tx_error_check;
|
|
|
|
/* hardware features */
|
|
unsigned no_psr:1; /* EtherC DO NOT have PSR */
|
|
unsigned apr:1; /* EtherC have APR */
|
|
unsigned mpr:1; /* EtherC have MPR */
|
|
unsigned tpauser:1; /* EtherC have TPAUSER */
|
|
unsigned bculr:1; /* EtherC have BCULR */
|
|
unsigned tsu:1; /* EtherC have TSU */
|
|
unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
|
|
unsigned rpadir:1; /* E-DMAC have RPADIR */
|
|
unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
|
|
unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
|
|
};
|
|
|
|
struct sh_eth_private {
|
|
struct platform_device *pdev;
|
|
struct sh_eth_cpu_data *cd;
|
|
const u16 *reg_offset;
|
|
void __iomem *tsu_addr;
|
|
dma_addr_t rx_desc_dma;
|
|
dma_addr_t tx_desc_dma;
|
|
struct sh_eth_rxdesc *rx_ring;
|
|
struct sh_eth_txdesc *tx_ring;
|
|
struct sk_buff **rx_skbuff;
|
|
struct sk_buff **tx_skbuff;
|
|
struct net_device_stats stats;
|
|
struct timer_list timer;
|
|
spinlock_t lock;
|
|
u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
|
|
u32 cur_tx, dirty_tx;
|
|
u32 rx_buf_sz; /* Based on MTU+slack. */
|
|
int edmac_endian;
|
|
/* MII transceiver section. */
|
|
u32 phy_id; /* PHY ID */
|
|
struct mii_bus *mii_bus; /* MDIO bus control */
|
|
struct phy_device *phydev; /* PHY device control */
|
|
enum phy_state link;
|
|
phy_interface_t phy_interface;
|
|
int msg_enable;
|
|
int speed;
|
|
int duplex;
|
|
u32 rx_int_var, tx_int_var; /* interrupt control variables */
|
|
char post_rx; /* POST receive */
|
|
char post_fw; /* POST forward */
|
|
struct net_device_stats tsu_stats; /* TSU forward status */
|
|
|
|
unsigned no_ether_link:1;
|
|
unsigned ether_link_active_low:1;
|
|
};
|
|
|
|
static inline void sh_eth_soft_swap(char *src, int len)
|
|
{
|
|
#ifdef __LITTLE_ENDIAN__
|
|
u32 *p = (u32 *)src;
|
|
u32 *maxp;
|
|
maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
|
|
|
|
for (; p < maxp; p++)
|
|
*p = swab32(*p);
|
|
#endif
|
|
}
|
|
|
|
static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
|
|
int enum_index)
|
|
{
|
|
struct sh_eth_private *mdp = netdev_priv(ndev);
|
|
|
|
writel(data, ndev->base_addr + mdp->reg_offset[enum_index]);
|
|
}
|
|
|
|
static inline unsigned long sh_eth_read(struct net_device *ndev,
|
|
int enum_index)
|
|
{
|
|
struct sh_eth_private *mdp = netdev_priv(ndev);
|
|
|
|
return readl(ndev->base_addr + mdp->reg_offset[enum_index]);
|
|
}
|
|
|
|
static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
|
|
unsigned long data, int enum_index)
|
|
{
|
|
writel(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
|
|
}
|
|
|
|
static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
|
|
int enum_index)
|
|
{
|
|
return readl(mdp->tsu_addr + mdp->reg_offset[enum_index]);
|
|
}
|
|
|
|
#endif /* #ifndef __SH_ETH_H__ */
|