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![Lior Dotan](/assets/img/avatar_default.png)
Fix the remaining variables that still had '_t' as a postfix and also a couple of checkpatch warnings. Signed-off-by: Lior Dotan <liodot@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
278 lines
11 KiB
C
278 lines
11 KiB
C
/*
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*
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* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* NO LICENSE TO ANY ALACRITECH PATENT CLAIM IS GRANTED BY ANY COPYRIGHT
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* LICENSE TO THIS OR OTHER SOFTWARE. THIS SOFTWARE MAY BE COVERED BY
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* ALACRITECH PATENTS INCLUDING BUT NOT LIMITED TO U.S. PATENT NOS. 6,226,680,
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* 6,247,060, 6,334,153, 6,389,479, 6,393,487, 6,427,171, 6,427,173
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* and 6,434,620.
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* THIS SOFTWARE IS NOT SUBJECT TO THE GNU GENERAL PUBLIC LICENSE (GPL).
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*
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* The views and conclusions contained in the software and
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* documentation are those of the authors and should not be
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* interpreted as representing official policies, either
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* expressed or implied, of Alacritech, Inc.
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*/
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#ifndef _SLIC_DUMP_H_
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#define _SLIC_DUMP_H_
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#define DEBUG_SUCCESS 0
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/***********************************************************************
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*
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* Utility processor register locations
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*
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**********************************************************************/
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#define UTILITY_RESET 0x0
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#define UTILITY_ISP_ADDR 0x4 /* Interrupt status Pointer */
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#define UTILITY_ISR_ADDR 0x8 /* Interrupt status Register */
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#define UTILITY_ICR_ADDR 0xc /* Interrupt Control Register */
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#define UTILITY_CPR_ADDR 0x10 /* Command Pointer Register */
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#define UTILITY_DPR_ADDR 0x14 /* Data Pointer Register */
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#define UTILITY_DMP_TRQ 0x18 /* Dump queue onto ALU for analyser */
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#define UTILITY_UPP_ADDR 0x1c /* Bits 63-32 of cmd/data pointer */
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/***********************************************************************
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*
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* INIC status register bits
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*
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***********************************************************************/
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#define SLIC_ISR_CC 0x10000000 /* Command complete - synchronous */
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#define SLIC_ISR_ERR 0x01000000 /* Command Error - synchronous */
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#define SLIC_ISR_CMD_MASK 0x11000000 /* Command status mask */
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#define SLIC_ISR_TPH 0x00080000 /* Transmit processor halted - async */
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#define SLIC_ISR_RPH 0x00040000 /* Receive processor halted - async */
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/***********************************************************************
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*
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* INIC Control register values
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*
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***********************************************************************/
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#define SLIC_ICR_OFF 0 /* Interrupts disabled */
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#define SLIC_ICR_ON 1 /* Interrupts enabled */
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#define SLIC_ICR_MASK 2 /* Interrupts masked */
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#define WRITE_DREG(reg, value, flush) \
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{ \
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writel((value), (reg)); \
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if ((flush)) { \
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mb(); \
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} \
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}
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/************************************************************************
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*
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* Command Format
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*
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* Each command contains a command byte which is defined as follows:
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*
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* bits: 7-3 2 1-0
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* ----------------------------------------------
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* command Alt. Proc Processor
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*
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************************************************************************/
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/*
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* Macro to create the command byte given the command, Alt. Proc, and
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* Processor values. Note that the macro assumes that the values are
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* preshifted. That is, the values for alt. proc are 0 for transmit and
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* 4 for receive.
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*/
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#define COMMAND_BYTE(command, alt_proc, proc) ((command) | (alt_proc) | (proc))
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/*
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* Command values
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*/
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#define CMD_HALT 0x0 /* Send a halt to the INIC */
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#define CMD_RUN 0x8 /* Start the halted INIC */
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#define CMD_STEP 0x10 /* Single step the inic */
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#define CMD_BREAK 0x18 /* Set a breakpoint - 8 byte command */
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#define CMD_RESET_BREAK 0x20 /* Reset a breakpoint - 8 byte cmd */
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#define CMD_DUMP 0x28 /* Dump INIC memory - 8 byte command */
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#define CMD_LOAD 0x30 /* Load INIC memory - 8 byte command */
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#define CMD_MAP 0x38 /* Map out a ROM instruction - 8 BC */
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#define CMD_CAM_OPS 0x38 /* perform ops on specific CAM */
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#define CMD_XMT 0x40 /* Transmit frame */
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#define CMD_RCV 0x48 /* Receive frame */
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/*
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* Alt. Proc values
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*
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* When the proc value is set to the utility processor, the Alt. Proc
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* specifies which processor handles the debugging.
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*/
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#define ALT_PROC_TRANSMIT 0x0
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#define ALT_PROC_RECEIVE 0x4
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/*
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* Proc values
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*/
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#define PROC_INVALID 0x0
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#define PROC_NONE 0x0 /* Gigabit use */
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#define PROC_TRANSMIT 0x1
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#define PROC_RECEIVE 0x2
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#define PROC_UTILITY 0x3
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/******************************************************************
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*
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* 8 byte command structure definitions
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*
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******************************************************************/
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/*
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* Break and Reset Break command structure
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*/
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struct BREAK {
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unsigned char command; /* Command word defined above */
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unsigned char resvd;
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ushort count; /* Number of executions before break */
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u32 addr; /* Address of break point */
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};
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/*
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* Dump and Load command structure
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*/
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struct dump_cmd {
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unsigned char cmd; /* Command word defined above */
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unsigned char desc; /* Descriptor values - defined below */
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ushort count; /* number of 4 byte words to be transferred */
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u32 addr; /* start address of dump or load */
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};
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/*
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* Receive or Transmit a frame.
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*/
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struct RCV_OR_XMT_FRAME {
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unsigned char command; /* Command word defined above */
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unsigned char MacId; /* Mac ID of interface - transmit only */
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ushort count; /* Length of frame in bytes */
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u32 pad; /* not used */
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};
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/*
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* Values of desc field in DUMP_OR_LOAD structure
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*/
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#define DESC_RFILE 0x0 /* Register file */
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#define DESC_SRAM 0x1 /* SRAM */
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#define DESC_DRAM 0x2 /* DRAM */
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#define DESC_QUEUE 0x3 /* queues */
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#define DESC_REG 0x4 /* General registers (pc, status, etc) */
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#define DESC_SENSE 0x5 /* Sense register */
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/* Descriptor field definitions for CMD_DUMP_CAM */
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#define DUMP_CAM_A 0
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#define DUMP_CAM_B 1 /* unused at present */
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#define DUMP_CAM_C 2
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#define DUMP_CAM_D 3
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#define SEARCH_CAM_A 4
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#define SEARCH_CAM_C 5
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/*
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* Map command to replace a command in ROM with a command in WCS
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*/
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struct MAP {
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unsigned char command; /* Command word defined above */
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unsigned char not_used[3];
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ushort map_to; /* Instruction address in WCS */
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ushort map_out; /* Instruction address in ROM */
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};
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/*
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* Misc definitions
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*/
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#define SLIC_MAX_QUEUE 32 /* Total # of queues on the INIC (0-31)*/
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#define SLIC_4MAX_REG 512 /* Total # of 4-port file-registers */
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#define SLIC_1MAX_REG 384 /* Total # of file-registers */
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#define SLIC_GBMAX_REG 1024 /* Total # of Gbit file-registers */
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#define SLIC_NUM_REG 32 /* non-file-registers = NUM_REG in tm-simba.h */
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#define SLIC_GB_CAMA_SZE 32
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#define SLIC_GB_CAMB_SZE 16
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#define SLIC_GB_CAMAB_SZE 32
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#define SLIC_GB_CAMC_SZE 16
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#define SLIC_GB_CAMD_SZE 16
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#define SLIC_GB_CAMCD_SZE 32
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/*
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* Coredump header structure
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*/
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struct CORE_Q {
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u32 queueOff; /* Offset of queue */
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u32 queuesize; /* size of queue */
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};
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#define DRIVER_NAME_SIZE 32
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struct sliccore_hdr {
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unsigned char driver_version[DRIVER_NAME_SIZE]; /* Driver version string */
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u32 RcvRegOff; /* Offset of receive registers */
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u32 RcvRegsize; /* size of receive registers */
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u32 XmtRegOff; /* Offset of transmit registers */
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u32 XmtRegsize; /* size of transmit registers */
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u32 FileRegOff; /* Offset of register file */
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u32 FileRegsize; /* size of register file */
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u32 SramOff; /* Offset of Sram */
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u32 Sramsize; /* size of Sram */
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u32 DramOff; /* Offset of Dram */
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u32 Dramsize; /* size of Dram */
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CORE_Q queues[SLIC_MAX_QUEUE]; /* size and offsets of queues */
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u32 CamAMOff; /* Offset of CAM A contents */
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u32 CamASize; /* Size of Cam A */
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u32 CamBMOff; /* Offset of CAM B contents */
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u32 CamBSize; /* Size of Cam B */
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u32 CamCMOff; /* Offset of CAM C contents */
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u32 CamCSize; /* Size of Cam C */
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u32 CamDMOff; /* Offset of CAM D contents */
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u32 CamDSize; /* Size of Cam D */
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};
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/*
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* definitions needed for our kernel-mode gdb stub.
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*/
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/***********************************************************************
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*
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* Definitions & Typedefs
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*
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**********************************************************************/
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#define BUFMAX 0x20000 /* 128k - size of input/output buffer */
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#define BUFMAXP2 5 /* 2**5 (32) 4K pages */
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#define IOCTL_SIMBA_BREAK _IOW('s', 0, unsigned long)
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/* #define IOCTL_SIMBA_INIT _IOW('s', 1, unsigned long) */
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#define IOCTL_SIMBA_KILL_TGT_PROC _IOW('s', 2, unsigned long)
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/***********************************************************************
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*
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* Global variables
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*
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***********************************************************************/
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#define THREADRECEIVE 1 /* bit 0 of StoppedThreads */
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#define THREADTRANSMIT 2 /* bit 1 of StoppedThreads */
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#define THREADBOTH 3 /* bit 0 and 1.. */
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#endif /* _SLIC_DUMP_H */
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