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3889ba7010
On contemporary platforms we don't use FIQ, and treat any stray FIQ as a fatal event. However, some platforms have an interrupt controller wired to FIQ, and need to handle FIQ as part of regular operation. So that we can support both cases dynamically, this patch updates the FIQ exception handling code to operate the same way as the IRQ handling code, with its own handle_arch_fiq handler. Where a root FIQ handler is not registered, an unexpected FIQ exception will trigger the default FIQ handler, which will panic() as today. Where a root FIQ handler is registered, handling of the FIQ is deferred to that handler. As el0_fiq_invalid_compat is supplanted by el0_fiq, the former is removed. For !CONFIG_COMPAT builds we never expect to take an exception from AArch32 EL0, so we keep the common el0_fiq_invalid handler. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Hector Martin <marcan@marcan.st> Cc: James Morse <james.morse@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210315115629.57191-7-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Based on arch/arm/kernel/irq.c
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*
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* Copyright (C) 1992 Linus Torvalds
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* Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
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* Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
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* Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and
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* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>.
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* Copyright (C) 2012 ARM Ltd.
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*/
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#include <linux/irq.h>
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#include <linux/memory.h>
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#include <linux/smp.h>
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#include <linux/hardirq.h>
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#include <linux/init.h>
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#include <linux/irqchip.h>
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#include <linux/kprobes.h>
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#include <linux/scs.h>
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#include <linux/seq_file.h>
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#include <linux/vmalloc.h>
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#include <asm/daifflags.h>
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#include <asm/vmap_stack.h>
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/* Only access this in an NMI enter/exit */
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DEFINE_PER_CPU(struct nmi_ctx, nmi_contexts);
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DEFINE_PER_CPU(unsigned long *, irq_stack_ptr);
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DECLARE_PER_CPU(unsigned long *, irq_shadow_call_stack_ptr);
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#ifdef CONFIG_SHADOW_CALL_STACK
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DEFINE_PER_CPU(unsigned long *, irq_shadow_call_stack_ptr);
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#endif
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static void init_irq_scs(void)
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{
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int cpu;
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if (!IS_ENABLED(CONFIG_SHADOW_CALL_STACK))
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return;
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for_each_possible_cpu(cpu)
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per_cpu(irq_shadow_call_stack_ptr, cpu) =
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scs_alloc(cpu_to_node(cpu));
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}
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#ifdef CONFIG_VMAP_STACK
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static void init_irq_stacks(void)
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{
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int cpu;
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unsigned long *p;
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for_each_possible_cpu(cpu) {
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p = arch_alloc_vmap_stack(IRQ_STACK_SIZE, cpu_to_node(cpu));
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per_cpu(irq_stack_ptr, cpu) = p;
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}
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}
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#else
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/* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
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DEFINE_PER_CPU_ALIGNED(unsigned long [IRQ_STACK_SIZE/sizeof(long)], irq_stack);
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static void init_irq_stacks(void)
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{
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int cpu;
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for_each_possible_cpu(cpu)
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per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu);
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}
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#endif
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static void default_handle_irq(struct pt_regs *regs)
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{
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panic("IRQ taken without a root IRQ handler\n");
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}
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static void default_handle_fiq(struct pt_regs *regs)
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{
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panic("FIQ taken without a root FIQ handler\n");
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}
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void (*handle_arch_irq)(struct pt_regs *) __ro_after_init = default_handle_irq;
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void (*handle_arch_fiq)(struct pt_regs *) __ro_after_init = default_handle_fiq;
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int __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
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{
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if (handle_arch_irq != default_handle_irq)
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return -EBUSY;
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handle_arch_irq = handle_irq;
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pr_info("Root IRQ handler: %ps\n", handle_irq);
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return 0;
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}
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int __init set_handle_fiq(void (*handle_fiq)(struct pt_regs *))
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{
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if (handle_arch_fiq != default_handle_fiq)
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return -EBUSY;
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handle_arch_fiq = handle_fiq;
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pr_info("Root FIQ handler: %ps\n", handle_fiq);
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return 0;
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}
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void __init init_IRQ(void)
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{
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init_irq_stacks();
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init_irq_scs();
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irqchip_init();
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if (system_uses_irq_prio_masking()) {
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/*
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* Now that we have a stack for our IRQ handler, set
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* the PMR/PSR pair to a consistent state.
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*/
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WARN_ON(read_sysreg(daif) & PSR_A_BIT);
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local_daif_restore(DAIF_PROCCTX_NOIRQ);
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}
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}
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