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![Dave Peterson](/assets/img/avatar_default.png)
- Fix code so we always hold mem_ctls_mutex while we are stepping through the list of mem_ctl_info structures. Otherwise bad things may happen if one task is stepping through the list while another task is modifying it. We may eventually want to use reference counting to manage the mem_ctl_info structures. In the meantime we may as well fix this bug. - Don't disable interrupts while we are walking the list of mem_ctl_info structures in check_mc_devices(). This is unnecessary. Signed-off-by: David S. Peterson <dsp@llnl.gov> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
402 lines
11 KiB
C
402 lines
11 KiB
C
/*
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* Radisys 82600 Embedded chipset Memory Controller kernel module
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* (C) 2005 EADS Astrium
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
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* Harbaugh, Dan Hollis <goemon at anime dot net> and others.
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*
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* $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
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*
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* Written with reference to 82600 High Integration Dual PCI System
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* Controller Data Book:
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* http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
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* references to this document given in []
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include "edac_mc.h"
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#define r82600_printk(level, fmt, arg...) \
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edac_printk(level, "r82600", fmt, ##arg)
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#define r82600_mc_printk(mci, level, fmt, arg...) \
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edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
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/* Radisys say "The 82600 integrates a main memory SDRAM controller that
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* supports up to four banks of memory. The four banks can support a mix of
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* sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
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* each of which can be any size from 16MB to 512MB. Both registered (control
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* signals buffered) and unbuffered DIMM types are supported. Mixing of
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* registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
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* is not allowed. The 82600 SDRAM interface operates at the same frequency as
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* the CPU bus, 66MHz, 100MHz or 133MHz."
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*/
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#define R82600_NR_CSROWS 4
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#define R82600_NR_CHANS 1
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#define R82600_NR_DIMMS 4
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#define R82600_BRIDGE_ID 0x8200
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/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
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#define R82600_DRAMC 0x57 /* Various SDRAM related control bits
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* all bits are R/W
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*
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* 7 SDRAM ISA Hole Enable
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* 6 Flash Page Mode Enable
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* 5 ECC Enable: 1=ECC 0=noECC
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* 4 DRAM DIMM Type: 1=
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* 3 BIOS Alias Disable
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* 2 SDRAM BIOS Flash Write Enable
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* 1:0 SDRAM Refresh Rate: 00=Disabled
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* 01=7.8usec (256Mbit SDRAMs)
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* 10=15.6us 11=125usec
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*/
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#define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
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* More SDRAM related control bits
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* all bits are R/W
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*
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* 15:8 Reserved.
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*
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* 7:5 Special SDRAM Mode Select
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*
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* 4 Force ECC
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*
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* 1=Drive ECC bits to 0 during
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* write cycles (i.e. ECC test mode)
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*
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* 0=Normal ECC functioning
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*
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* 3 Enhanced Paging Enable
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*
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* 2 CAS# Latency 0=3clks 1=2clks
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*
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* 1 RAS# to CAS# Delay 0=3 1=2
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*
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* 0 RAS# Precharge 0=3 1=2
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*/
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#define R82600_EAP 0x80 /* ECC Error Address Pointer Register
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*
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* 31 Disable Hardware Scrubbing (RW)
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* 0=Scrub on corrected read
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* 1=Don't scrub on corrected read
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*
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* 30:12 Error Address Pointer (RO)
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* Upper 19 bits of error address
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*
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* 11:4 Syndrome Bits (RO)
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*
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* 3 BSERR# on multibit error (RW)
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* 1=enable 0=disable
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*
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* 2 NMI on Single Bit Eror (RW)
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* 1=NMI triggered by SBE n.b. other
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* prerequeists
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* 0=NMI not triggered
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*
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* 1 MBE (R/WC)
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* read 1=MBE at EAP (see above)
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* read 0=no MBE, or SBE occurred first
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* write 1=Clear MBE status (must also
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* clear SBE)
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* write 0=NOP
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*
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* 1 SBE (R/WC)
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* read 1=SBE at EAP (see above)
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* read 0=no SBE, or MBE occurred first
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* write 1=Clear SBE status (must also
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* clear MBE)
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* write 0=NOP
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*/
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#define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundry Address
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* Registers
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*
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* 7:0 Address lines 30:24 - upper limit of
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* each row [p57]
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*/
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struct r82600_error_info {
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u32 eapr;
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};
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static unsigned int disable_hardware_scrub = 0;
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static void r82600_get_error_info (struct mem_ctl_info *mci,
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struct r82600_error_info *info)
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{
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pci_read_config_dword(mci->pdev, R82600_EAP, &info->eapr);
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if (info->eapr & BIT(0))
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/* Clear error to allow next error to be reported [p.62] */
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pci_write_bits32(mci->pdev, R82600_EAP,
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((u32) BIT(0) & (u32) BIT(1)),
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((u32) BIT(0) & (u32) BIT(1)));
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if (info->eapr & BIT(1))
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/* Clear error to allow next error to be reported [p.62] */
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pci_write_bits32(mci->pdev, R82600_EAP,
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((u32) BIT(0) & (u32) BIT(1)),
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((u32) BIT(0) & (u32) BIT(1)));
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}
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static int r82600_process_error_info (struct mem_ctl_info *mci,
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struct r82600_error_info *info, int handle_errors)
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{
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int error_found;
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u32 eapaddr, page;
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u32 syndrome;
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error_found = 0;
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/* bits 30:12 store the upper 19 bits of the 32 bit error address */
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eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
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/* Syndrome in bits 11:4 [p.62] */
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syndrome = (info->eapr >> 4) & 0xFF;
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/* the R82600 reports at less than page *
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* granularity (upper 19 bits only) */
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page = eapaddr >> PAGE_SHIFT;
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if (info->eapr & BIT(0)) { /* CE? */
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error_found = 1;
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if (handle_errors)
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edac_mc_handle_ce(
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mci, page, 0, /* not avail */
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syndrome,
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edac_mc_find_csrow_by_page(mci, page),
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0, /* channel */
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mci->ctl_name);
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}
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if (info->eapr & BIT(1)) { /* UE? */
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error_found = 1;
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if (handle_errors)
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/* 82600 doesn't give enough info */
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edac_mc_handle_ue(mci, page, 0,
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edac_mc_find_csrow_by_page(mci, page),
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mci->ctl_name);
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}
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return error_found;
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}
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static void r82600_check(struct mem_ctl_info *mci)
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{
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struct r82600_error_info info;
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debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
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r82600_get_error_info(mci, &info);
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r82600_process_error_info(mci, &info, 1);
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}
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static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
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{
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int rc = -ENODEV;
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int index;
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struct mem_ctl_info *mci = NULL;
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u8 dramcr;
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u32 ecc_on;
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u32 reg_sdram;
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u32 eapr;
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u32 scrub_disabled;
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u32 sdram_refresh_rate;
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u32 row_high_limit_last = 0;
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struct r82600_error_info discard;
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debugf0("%s()\n", __func__);
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pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
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pci_read_config_dword(pdev, R82600_EAP, &eapr);
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ecc_on = dramcr & BIT(5);
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reg_sdram = dramcr & BIT(4);
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scrub_disabled = eapr & BIT(31);
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sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
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debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
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sdram_refresh_rate);
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debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
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mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);
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if (mci == NULL) {
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rc = -ENOMEM;
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goto fail;
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}
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debugf0("%s(): mci = %p\n", __func__, mci);
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mci->pdev = pdev;
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mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
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/* FIXME try to work out if the chip leads have been *
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* used for COM2 instead on this board? [MA6?] MAYBE: */
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/* On the R82600, the pins for memory bits 72:65 - i.e. the *
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* EC bits are shared with the pins for COM2 (!), so if COM2 *
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* is enabled, we assume COM2 is wired up, and thus no EDAC *
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* is possible. */
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mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
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if (ecc_on) {
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if (scrub_disabled)
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debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
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"%#0x\n", __func__, mci, eapr);
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} else
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mci->edac_cap = EDAC_FLAG_NONE;
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = "$Revision: 1.1.2.6 $";
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mci->ctl_name = "R82600";
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mci->edac_check = r82600_check;
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mci->ctl_page_to_phys = NULL;
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for (index = 0; index < mci->nr_csrows; index++) {
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struct csrow_info *csrow = &mci->csrows[index];
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u8 drbar; /* sDram Row Boundry Address Register */
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u32 row_high_limit;
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u32 row_base;
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/* find the DRAM Chip Select Base address and mask */
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pci_read_config_byte(mci->pdev, R82600_DRBA + index, &drbar);
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debugf1("MC%d: %s() Row=%d DRBA = %#0x\n", mci->mc_idx,
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__func__, index, drbar);
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row_high_limit = ((u32) drbar << 24);
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/* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
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debugf1("MC%d: %s() Row=%d, Boundry Address=%#0x, Last = "
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"%#0x \n", mci->mc_idx, __func__, index,
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row_high_limit, row_high_limit_last);
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/* Empty row [p.57] */
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if (row_high_limit == row_high_limit_last)
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continue;
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row_base = row_high_limit_last;
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csrow->first_page = row_base >> PAGE_SHIFT;
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csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
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csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
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/* Error address is top 19 bits - so granularity is *
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* 14 bits */
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csrow->grain = 1 << 14;
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csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
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/* FIXME - check that this is unknowable with this chipset */
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csrow->dtype = DEV_UNKNOWN;
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/* Mode is global on 82600 */
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csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
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row_high_limit_last = row_high_limit;
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}
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r82600_get_error_info(mci, &discard); /* clear counters */
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if (edac_mc_add_mc(mci)) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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goto fail;
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}
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/* get this far and it's successful */
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if (disable_hardware_scrub) {
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debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
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__func__);
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pci_write_bits32(mci->pdev, R82600_EAP, BIT(31), BIT(31));
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}
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debugf3("%s(): success\n", __func__);
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return 0;
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fail:
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if (mci)
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edac_mc_free(mci);
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return rc;
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}
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/* returns count (>= 0), or negative on error */
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static int __devinit r82600_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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debugf0("%s()\n", __func__);
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/* don't need to call pci_device_enable() */
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return r82600_probe1(pdev, ent->driver_data);
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}
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static void __devexit r82600_remove_one(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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debugf0("%s()\n", __func__);
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if ((mci = edac_mc_del_mc(pdev)) == NULL)
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return;
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edac_mc_free(mci);
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}
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static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
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{PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)},
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{0,} /* 0 terminated list. */
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};
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MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
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static struct pci_driver r82600_driver = {
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.name = EDAC_MOD_STR,
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.probe = r82600_init_one,
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.remove = __devexit_p(r82600_remove_one),
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.id_table = r82600_pci_tbl,
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};
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static int __init r82600_init(void)
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{
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return pci_register_driver(&r82600_driver);
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}
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static void __exit r82600_exit(void)
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{
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pci_unregister_driver(&r82600_driver);
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}
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module_init(r82600_init);
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module_exit(r82600_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
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"on behalf of EADS Astrium");
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MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
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module_param(disable_hardware_scrub, bool, 0644);
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MODULE_PARM_DESC(disable_hardware_scrub,
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"If set, disable the chipset's automatic scrub for CEs");
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