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![Hannes Reinecke](/assets/img/avatar_default.png)
Drop pointless VPRINTK() calls for entering routines and setting up sg tables. And while we're at it, remove the disabled debugging messages. Signed-off-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
608 lines
15 KiB
C
608 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* pdc_adma.c - Pacific Digital Corporation ADMA
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*
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* Maintained by: Tejun Heo <tj@kernel.org>
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*
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* Copyright 2005 Mark Lord
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/driver-api/libata.rst
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*
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* Supports ATA disks in single-packet ADMA mode.
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* Uses PIO for everything else.
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*
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* TODO: Use ADMA transfers for ATAPI devices, when possible.
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* This requires careful attention to a number of quirks of the chip.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/gfp.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pdc_adma"
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#define DRV_VERSION "1.0"
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/* macro to calculate base address for ATA regs */
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#define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
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/* macro to calculate base address for ADMA regs */
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#define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
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/* macro to obtain addresses from ata_port */
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#define ADMA_PORT_REGS(ap) \
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ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
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enum {
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ADMA_MMIO_BAR = 4,
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ADMA_PORTS = 2,
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ADMA_CPB_BYTES = 40,
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ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
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ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
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ADMA_DMA_BOUNDARY = 0xffffffff,
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/* global register offsets */
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ADMA_MODE_LOCK = 0x00c7,
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/* per-channel register offsets */
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ADMA_CONTROL = 0x0000, /* ADMA control */
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ADMA_STATUS = 0x0002, /* ADMA status */
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ADMA_CPB_COUNT = 0x0004, /* CPB count */
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ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
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ADMA_CPB_NEXT = 0x000c, /* next CPB address */
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ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
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ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
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ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
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/* ADMA_CONTROL register bits */
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aNIEN = (1 << 8), /* irq mask: 1==masked */
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aGO = (1 << 7), /* packet trigger ("Go!") */
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aRSTADM = (1 << 5), /* ADMA logic reset */
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aPIOMD4 = 0x0003, /* PIO mode 4 */
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/* ADMA_STATUS register bits */
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aPSD = (1 << 6),
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aUIRQ = (1 << 4),
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aPERR = (1 << 0),
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/* CPB bits */
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cDONE = (1 << 0),
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cATERR = (1 << 3),
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cVLD = (1 << 0),
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cDAT = (1 << 2),
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cIEN = (1 << 3),
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/* PRD bits */
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pORD = (1 << 4),
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pDIRO = (1 << 5),
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pEND = (1 << 7),
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/* ATA register flags */
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rIGN = (1 << 5),
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rEND = (1 << 7),
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/* ATA register addresses */
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ADMA_REGS_CONTROL = 0x0e,
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ADMA_REGS_SECTOR_COUNT = 0x12,
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ADMA_REGS_LBA_LOW = 0x13,
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ADMA_REGS_LBA_MID = 0x14,
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ADMA_REGS_LBA_HIGH = 0x15,
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ADMA_REGS_DEVICE = 0x16,
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ADMA_REGS_COMMAND = 0x17,
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/* PCI device IDs */
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board_1841_idx = 0, /* ADMA 2-port controller */
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};
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typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
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struct adma_port_priv {
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u8 *pkt;
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dma_addr_t pkt_dma;
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adma_state_t state;
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};
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static int adma_ata_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent);
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static int adma_port_start(struct ata_port *ap);
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static void adma_port_stop(struct ata_port *ap);
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static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc);
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static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
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static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
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static void adma_freeze(struct ata_port *ap);
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static void adma_thaw(struct ata_port *ap);
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static int adma_prereset(struct ata_link *link, unsigned long deadline);
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static struct scsi_host_template adma_ata_sht = {
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ATA_BASE_SHT(DRV_NAME),
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.sg_tablesize = LIBATA_MAX_PRD,
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.dma_boundary = ADMA_DMA_BOUNDARY,
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};
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static struct ata_port_operations adma_ata_ops = {
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.inherits = &ata_sff_port_ops,
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.lost_interrupt = ATA_OP_NULL,
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.check_atapi_dma = adma_check_atapi_dma,
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.qc_prep = adma_qc_prep,
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.qc_issue = adma_qc_issue,
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.freeze = adma_freeze,
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.thaw = adma_thaw,
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.prereset = adma_prereset,
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.port_start = adma_port_start,
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.port_stop = adma_port_stop,
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};
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static struct ata_port_info adma_port_info[] = {
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/* board_1841_idx */
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{
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
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.pio_mask = ATA_PIO4_ONLY,
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.udma_mask = ATA_UDMA4,
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.port_ops = &adma_ata_ops,
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},
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};
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static const struct pci_device_id adma_ata_pci_tbl[] = {
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{ PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
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{ } /* terminate list */
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};
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static struct pci_driver adma_ata_pci_driver = {
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.name = DRV_NAME,
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.id_table = adma_ata_pci_tbl,
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.probe = adma_ata_init_one,
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.remove = ata_pci_remove_one,
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};
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static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
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{
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return 1; /* ATAPI DMA not yet supported */
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}
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static void adma_reset_engine(struct ata_port *ap)
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{
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void __iomem *chan = ADMA_PORT_REGS(ap);
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/* reset ADMA to idle state */
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writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
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udelay(2);
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writew(aPIOMD4, chan + ADMA_CONTROL);
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udelay(2);
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}
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static void adma_reinit_engine(struct ata_port *ap)
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{
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struct adma_port_priv *pp = ap->private_data;
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void __iomem *chan = ADMA_PORT_REGS(ap);
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/* mask/clear ATA interrupts */
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writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
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ata_sff_check_status(ap);
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/* reset the ADMA engine */
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adma_reset_engine(ap);
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/* set in-FIFO threshold to 0x100 */
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writew(0x100, chan + ADMA_FIFO_IN);
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/* set CPB pointer */
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writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
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/* set out-FIFO threshold to 0x100 */
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writew(0x100, chan + ADMA_FIFO_OUT);
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/* set CPB count */
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writew(1, chan + ADMA_CPB_COUNT);
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/* read/discard ADMA status */
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readb(chan + ADMA_STATUS);
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}
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static inline void adma_enter_reg_mode(struct ata_port *ap)
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{
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void __iomem *chan = ADMA_PORT_REGS(ap);
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writew(aPIOMD4, chan + ADMA_CONTROL);
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readb(chan + ADMA_STATUS); /* flush */
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}
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static void adma_freeze(struct ata_port *ap)
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{
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void __iomem *chan = ADMA_PORT_REGS(ap);
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/* mask/clear ATA interrupts */
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writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
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ata_sff_check_status(ap);
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/* reset ADMA to idle state */
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writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
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udelay(2);
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writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
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udelay(2);
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}
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static void adma_thaw(struct ata_port *ap)
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{
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adma_reinit_engine(ap);
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}
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static int adma_prereset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct adma_port_priv *pp = ap->private_data;
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if (pp->state != adma_state_idle) /* healthy paranoia */
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pp->state = adma_state_mmio;
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adma_reinit_engine(ap);
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return ata_sff_prereset(link, deadline);
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}
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static int adma_fill_sg(struct ata_queued_cmd *qc)
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{
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struct scatterlist *sg;
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struct ata_port *ap = qc->ap;
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struct adma_port_priv *pp = ap->private_data;
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u8 *buf = pp->pkt, *last_buf = NULL;
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int i = (2 + buf[3]) * 8;
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u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
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unsigned int si;
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for_each_sg(qc->sg, sg, qc->n_elem, si) {
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u32 addr;
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u32 len;
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addr = (u32)sg_dma_address(sg);
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*(__le32 *)(buf + i) = cpu_to_le32(addr);
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i += 4;
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len = sg_dma_len(sg) >> 3;
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*(__le32 *)(buf + i) = cpu_to_le32(len);
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i += 4;
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last_buf = &buf[i];
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buf[i++] = pFLAGS;
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buf[i++] = qc->dev->dma_mode & 0xf;
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buf[i++] = 0; /* pPKLW */
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buf[i++] = 0; /* reserved */
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*(__le32 *)(buf + i) =
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(pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
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i += 4;
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}
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if (likely(last_buf))
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*last_buf |= pEND;
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return i;
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}
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static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc)
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{
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struct adma_port_priv *pp = qc->ap->private_data;
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u8 *buf = pp->pkt;
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u32 pkt_dma = (u32)pp->pkt_dma;
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int i = 0;
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adma_enter_reg_mode(qc->ap);
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if (qc->tf.protocol != ATA_PROT_DMA)
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return AC_ERR_OK;
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buf[i++] = 0; /* Response flags */
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buf[i++] = 0; /* reserved */
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buf[i++] = cVLD | cDAT | cIEN;
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i++; /* cLEN, gets filled in below */
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*(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
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i += 4; /* cNCPB */
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i += 4; /* cPRD, gets filled in below */
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buf[i++] = 0; /* reserved */
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buf[i++] = 0; /* reserved */
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buf[i++] = 0; /* reserved */
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buf[i++] = 0; /* reserved */
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/* ATA registers; must be a multiple of 4 */
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buf[i++] = qc->tf.device;
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buf[i++] = ADMA_REGS_DEVICE;
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if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
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buf[i++] = qc->tf.hob_nsect;
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buf[i++] = ADMA_REGS_SECTOR_COUNT;
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buf[i++] = qc->tf.hob_lbal;
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buf[i++] = ADMA_REGS_LBA_LOW;
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buf[i++] = qc->tf.hob_lbam;
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buf[i++] = ADMA_REGS_LBA_MID;
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buf[i++] = qc->tf.hob_lbah;
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buf[i++] = ADMA_REGS_LBA_HIGH;
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}
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buf[i++] = qc->tf.nsect;
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buf[i++] = ADMA_REGS_SECTOR_COUNT;
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buf[i++] = qc->tf.lbal;
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buf[i++] = ADMA_REGS_LBA_LOW;
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buf[i++] = qc->tf.lbam;
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buf[i++] = ADMA_REGS_LBA_MID;
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buf[i++] = qc->tf.lbah;
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buf[i++] = ADMA_REGS_LBA_HIGH;
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buf[i++] = 0;
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buf[i++] = ADMA_REGS_CONTROL;
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buf[i++] = rIGN;
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buf[i++] = 0;
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buf[i++] = qc->tf.command;
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buf[i++] = ADMA_REGS_COMMAND | rEND;
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buf[3] = (i >> 3) - 2; /* cLEN */
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*(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
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i = adma_fill_sg(qc);
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wmb(); /* flush PRDs and pkt to memory */
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return AC_ERR_OK;
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}
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static inline void adma_packet_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *chan = ADMA_PORT_REGS(ap);
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/* fire up the ADMA engine */
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writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
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}
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static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
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{
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struct adma_port_priv *pp = qc->ap->private_data;
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switch (qc->tf.protocol) {
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case ATA_PROT_DMA:
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pp->state = adma_state_pkt;
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adma_packet_start(qc);
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return 0;
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case ATAPI_PROT_DMA:
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BUG();
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break;
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default:
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break;
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}
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pp->state = adma_state_mmio;
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return ata_sff_qc_issue(qc);
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}
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static inline unsigned int adma_intr_pkt(struct ata_host *host)
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{
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unsigned int handled = 0, port_no;
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for (port_no = 0; port_no < host->n_ports; ++port_no) {
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struct ata_port *ap = host->ports[port_no];
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struct adma_port_priv *pp;
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struct ata_queued_cmd *qc;
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void __iomem *chan = ADMA_PORT_REGS(ap);
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u8 status = readb(chan + ADMA_STATUS);
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if (status == 0)
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continue;
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handled = 1;
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adma_enter_reg_mode(ap);
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pp = ap->private_data;
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if (!pp || pp->state != adma_state_pkt)
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continue;
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qc = ata_qc_from_tag(ap, ap->link.active_tag);
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if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
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if (status & aPERR)
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qc->err_mask |= AC_ERR_HOST_BUS;
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else if ((status & (aPSD | aUIRQ)))
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qc->err_mask |= AC_ERR_OTHER;
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if (pp->pkt[0] & cATERR)
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qc->err_mask |= AC_ERR_DEV;
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else if (pp->pkt[0] != cDONE)
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qc->err_mask |= AC_ERR_OTHER;
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if (!qc->err_mask)
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ata_qc_complete(qc);
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else {
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struct ata_eh_info *ehi = &ap->link.eh_info;
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ata_ehi_clear_desc(ehi);
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ata_ehi_push_desc(ehi,
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"ADMA-status 0x%02X", status);
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ata_ehi_push_desc(ehi,
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"pkt[0] 0x%02X", pp->pkt[0]);
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if (qc->err_mask == AC_ERR_DEV)
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ata_port_abort(ap);
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else
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ata_port_freeze(ap);
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}
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}
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}
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return handled;
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}
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static inline unsigned int adma_intr_mmio(struct ata_host *host)
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{
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unsigned int handled = 0, port_no;
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for (port_no = 0; port_no < host->n_ports; ++port_no) {
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struct ata_port *ap = host->ports[port_no];
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struct adma_port_priv *pp = ap->private_data;
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struct ata_queued_cmd *qc;
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if (!pp || pp->state != adma_state_mmio)
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continue;
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qc = ata_qc_from_tag(ap, ap->link.active_tag);
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if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
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/* check main status, clearing INTRQ */
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u8 status = ata_sff_check_status(ap);
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if ((status & ATA_BUSY))
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continue;
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/* complete taskfile transaction */
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pp->state = adma_state_idle;
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qc->err_mask |= ac_err_mask(status);
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if (!qc->err_mask)
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ata_qc_complete(qc);
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else {
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struct ata_eh_info *ehi = &ap->link.eh_info;
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ata_ehi_clear_desc(ehi);
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ata_ehi_push_desc(ehi, "status 0x%02X", status);
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if (qc->err_mask == AC_ERR_DEV)
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ata_port_abort(ap);
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else
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ata_port_freeze(ap);
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}
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handled = 1;
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}
|
|
}
|
|
return handled;
|
|
}
|
|
|
|
static irqreturn_t adma_intr(int irq, void *dev_instance)
|
|
{
|
|
struct ata_host *host = dev_instance;
|
|
unsigned int handled = 0;
|
|
|
|
spin_lock(&host->lock);
|
|
handled = adma_intr_pkt(host) | adma_intr_mmio(host);
|
|
spin_unlock(&host->lock);
|
|
|
|
return IRQ_RETVAL(handled);
|
|
}
|
|
|
|
static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
|
|
{
|
|
port->cmd_addr =
|
|
port->data_addr = base + 0x000;
|
|
port->error_addr =
|
|
port->feature_addr = base + 0x004;
|
|
port->nsect_addr = base + 0x008;
|
|
port->lbal_addr = base + 0x00c;
|
|
port->lbam_addr = base + 0x010;
|
|
port->lbah_addr = base + 0x014;
|
|
port->device_addr = base + 0x018;
|
|
port->status_addr =
|
|
port->command_addr = base + 0x01c;
|
|
port->altstatus_addr =
|
|
port->ctl_addr = base + 0x038;
|
|
}
|
|
|
|
static int adma_port_start(struct ata_port *ap)
|
|
{
|
|
struct device *dev = ap->host->dev;
|
|
struct adma_port_priv *pp;
|
|
|
|
adma_enter_reg_mode(ap);
|
|
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
|
|
if (!pp)
|
|
return -ENOMEM;
|
|
pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
|
|
GFP_KERNEL);
|
|
if (!pp->pkt)
|
|
return -ENOMEM;
|
|
/* paranoia? */
|
|
if ((pp->pkt_dma & 7) != 0) {
|
|
ata_port_err(ap, "bad alignment for pp->pkt_dma: %08x\n",
|
|
(u32)pp->pkt_dma);
|
|
return -ENOMEM;
|
|
}
|
|
ap->private_data = pp;
|
|
adma_reinit_engine(ap);
|
|
return 0;
|
|
}
|
|
|
|
static void adma_port_stop(struct ata_port *ap)
|
|
{
|
|
adma_reset_engine(ap);
|
|
}
|
|
|
|
static void adma_host_init(struct ata_host *host, unsigned int chip_id)
|
|
{
|
|
unsigned int port_no;
|
|
|
|
/* enable/lock aGO operation */
|
|
writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
|
|
|
|
/* reset the ADMA logic */
|
|
for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
|
|
adma_reset_engine(host->ports[port_no]);
|
|
}
|
|
|
|
static int adma_ata_init_one(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
|
const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
|
|
struct ata_host *host;
|
|
void __iomem *mmio_base;
|
|
int rc, port_no;
|
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
|
|
|
/* alloc host */
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
|
|
/* acquire resources and fill host */
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
|
|
return -ENODEV;
|
|
|
|
rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
|
|
if (rc)
|
|
return rc;
|
|
host->iomap = pcim_iomap_table(pdev);
|
|
mmio_base = host->iomap[ADMA_MMIO_BAR];
|
|
|
|
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
|
if (rc) {
|
|
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
|
|
return rc;
|
|
}
|
|
|
|
for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
|
|
struct ata_port *ap = host->ports[port_no];
|
|
void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
|
|
unsigned int offset = port_base - mmio_base;
|
|
|
|
adma_ata_setup_port(&ap->ioaddr, port_base);
|
|
|
|
ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
|
|
ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
|
|
}
|
|
|
|
/* initialize adapter */
|
|
adma_host_init(host, board_idx);
|
|
|
|
pci_set_master(pdev);
|
|
return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
|
|
&adma_ata_sht);
|
|
}
|
|
|
|
module_pci_driver(adma_ata_pci_driver);
|
|
|
|
MODULE_AUTHOR("Mark Lord");
|
|
MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
|
|
MODULE_VERSION(DRV_VERSION);
|