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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define MHZ (1000 * 1000)
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#define BASE_CPU_SHIFT 1
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#define BASE_CPU_MASK 0x7F
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#define CPU_AHB_SHIFT 12
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#define CPU_AHB_MASK 0x07
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#define FIXED_BASE_SHIFT 8
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#define FIXED_BASE_MASK 0x01
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#define CLASSIC_BASE_SHIFT 16
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#define CLASSIC_BASE_MASK 0x1F
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#define CX_BASE_SHIFT 15
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#define CX_BASE_MASK 0x3F
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#define CX_UNKNOWN_SHIFT 21
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#define CX_UNKNOWN_MASK 0x03
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struct nspire_clk_info {
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u32 base_clock;
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u16 base_cpu_ratio;
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u16 base_ahb_ratio;
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};
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#define EXTRACT(var, prop) (((var)>>prop##_SHIFT) & prop##_MASK)
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static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk)
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{
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if (EXTRACT(val, FIXED_BASE))
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clk->base_clock = 48 * MHZ;
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else
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clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ;
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clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN);
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clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
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}
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static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk)
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{
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if (EXTRACT(val, FIXED_BASE))
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clk->base_clock = 27 * MHZ;
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else
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clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ;
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clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2;
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clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1);
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}
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static void __init nspire_ahbdiv_setup(struct device_node *node,
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void (*get_clkinfo)(u32, struct nspire_clk_info *))
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{
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u32 val;
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void __iomem *io;
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struct clk_hw *hw;
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const char *clk_name = node->name;
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const char *parent_name;
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struct nspire_clk_info info;
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io = of_iomap(node, 0);
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if (!io)
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return;
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val = readl(io);
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iounmap(io);
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get_clkinfo(val, &info);
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of_property_read_string(node, "clock-output-names", &clk_name);
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parent_name = of_clk_get_parent_name(node, 0);
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hw = clk_hw_register_fixed_factor(NULL, clk_name, parent_name, 0,
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1, info.base_ahb_ratio);
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if (!IS_ERR(hw))
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of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
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}
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static void __init nspire_ahbdiv_setup_cx(struct device_node *node)
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{
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nspire_ahbdiv_setup(node, nspire_clkinfo_cx);
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}
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static void __init nspire_ahbdiv_setup_classic(struct device_node *node)
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{
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nspire_ahbdiv_setup(node, nspire_clkinfo_classic);
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}
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CLK_OF_DECLARE(nspire_ahbdiv_cx, "lsi,nspire-cx-ahb-divider",
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nspire_ahbdiv_setup_cx);
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CLK_OF_DECLARE(nspire_ahbdiv_classic, "lsi,nspire-classic-ahb-divider",
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nspire_ahbdiv_setup_classic);
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static void __init nspire_clk_setup(struct device_node *node,
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void (*get_clkinfo)(u32, struct nspire_clk_info *))
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{
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u32 val;
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void __iomem *io;
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struct clk_hw *hw;
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const char *clk_name = node->name;
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struct nspire_clk_info info;
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io = of_iomap(node, 0);
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if (!io)
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return;
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val = readl(io);
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iounmap(io);
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get_clkinfo(val, &info);
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of_property_read_string(node, "clock-output-names", &clk_name);
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hw = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0,
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info.base_clock);
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if (!IS_ERR(hw))
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of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
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else
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return;
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pr_info("TI-NSPIRE Base: %uMHz CPU: %uMHz AHB: %uMHz\n",
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info.base_clock / MHZ,
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info.base_clock / info.base_cpu_ratio / MHZ,
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info.base_clock / info.base_ahb_ratio / MHZ);
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}
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static void __init nspire_clk_setup_cx(struct device_node *node)
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{
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nspire_clk_setup(node, nspire_clkinfo_cx);
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}
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static void __init nspire_clk_setup_classic(struct device_node *node)
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{
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nspire_clk_setup(node, nspire_clkinfo_classic);
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}
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CLK_OF_DECLARE(nspire_clk_cx, "lsi,nspire-cx-clock", nspire_clk_setup_cx);
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CLK_OF_DECLARE(nspire_clk_classic, "lsi,nspire-classic-clock",
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nspire_clk_setup_classic);
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