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The Ux500 PRCC (peripheral reset and clock controller) can also control reset of the IP blocks, not just clocks. As the PRCC is probed as a clock controller and we have other platforms implementing combined clock and reset controllers, follow this pattern and implement the PRCC rest controller as part of the clock driver. The reset controller needs to be selected from the machine as Ux500 has traditionally selected its mandatory subsystem prerequisites from there. Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.org Acked-by: Ulf Hansson <ulf.hansson@linaro.org> [sboyd@kernel.org: Dropped allocation error message] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
19 lines
336 B
C
19 lines
336 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __PRCC_H
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#define __PRCC_H
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#define PRCC_NUM_PERIPH_CLUSTERS 6
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#define PRCC_PERIPHS_PER_CLUSTER 32
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/* CLKRST4 is missing making it hard to index things */
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enum clkrst_index {
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CLKRST1_INDEX = 0,
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CLKRST2_INDEX,
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CLKRST3_INDEX,
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CLKRST5_INDEX,
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CLKRST6_INDEX,
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CLKRST_MAX,
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};
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#endif
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