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![Sumit Gupta](/assets/img/avatar_default.png)
This patch adds driver support for Tegra234 cpufreq. Tegra234 has per core MMIO registers instead of system registers for cpu frequency requests and to read the counters for re-constructing the cpu frequency. Also, MPIDR affinity info in Tegra234 is different from Tegra194. Added ops hooks and soc data for Tegra234. This will help to easily add variants of Tegra234 and future SoC's which use similar logic to {get|set} the cpu frequency. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
609 lines
17 KiB
C
609 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved
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*/
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <asm/smp_plat.h>
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#include <soc/tegra/bpmp.h>
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#include <soc/tegra/bpmp-abi.h>
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#define KHZ 1000
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#define REF_CLK_MHZ 408 /* 408 MHz */
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#define US_DELAY 500
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#define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
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#define MAX_CNT ~0U
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#define NDIV_MASK 0x1FF
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#define CORE_OFFSET(cpu) (cpu * 8)
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#define CMU_CLKS_BASE 0x2000
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#define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu))
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#define MMCRAB_CLUSTER_BASE(cl) (0x30000 + (cl * 0x10000))
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#define CLUSTER_ACTMON_BASE(data, cl) \
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(data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base))
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#define CORE_ACTMON_CNTR_REG(data, cl, cpu) (CLUSTER_ACTMON_BASE(data, cl) + CORE_OFFSET(cpu))
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/* cpufreq transisition latency */
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#define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */
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enum cluster {
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CLUSTER0,
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CLUSTER1,
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CLUSTER2,
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CLUSTER3,
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MAX_CLUSTERS,
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};
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struct tegra_cpu_ctr {
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u32 cpu;
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u32 coreclk_cnt, last_coreclk_cnt;
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u32 refclk_cnt, last_refclk_cnt;
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};
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struct read_counters_work {
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struct work_struct work;
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struct tegra_cpu_ctr c;
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};
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struct tegra_cpufreq_ops {
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void (*read_counters)(struct tegra_cpu_ctr *c);
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void (*set_cpu_ndiv)(struct cpufreq_policy *policy, u64 ndiv);
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void (*get_cpu_cluster_id)(u32 cpu, u32 *cpuid, u32 *clusterid);
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int (*get_cpu_ndiv)(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv);
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};
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struct tegra_cpufreq_soc {
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struct tegra_cpufreq_ops *ops;
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int maxcpus_per_cluster;
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phys_addr_t actmon_cntr_base;
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};
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struct tegra194_cpufreq_data {
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void __iomem *regs;
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size_t num_clusters;
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struct cpufreq_frequency_table **tables;
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const struct tegra_cpufreq_soc *soc;
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};
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static struct workqueue_struct *read_counters_wq;
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static void tegra_get_cpu_mpidr(void *mpidr)
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{
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*((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
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}
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static void tegra234_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid)
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{
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u64 mpidr;
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smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true);
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if (cpuid)
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*cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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if (clusterid)
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*clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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}
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static int tegra234_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv)
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{
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struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
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void __iomem *freq_core_reg;
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u64 mpidr_id;
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/* use physical id to get address of per core frequency register */
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mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid;
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freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id);
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*ndiv = readl(freq_core_reg) & NDIV_MASK;
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return 0;
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}
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static void tegra234_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv)
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{
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struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
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void __iomem *freq_core_reg;
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u32 cpu, cpuid, clusterid;
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u64 mpidr_id;
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for_each_cpu_and(cpu, policy->cpus, cpu_online_mask) {
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data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid);
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/* use physical id to get address of per core frequency register */
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mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid;
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freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id);
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writel(ndiv, freq_core_reg);
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}
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}
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/*
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* This register provides access to two counter values with a single
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* 64-bit read. The counter values are used to determine the average
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* actual frequency a core has run at over a period of time.
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* [63:32] PLLP counter: Counts at fixed frequency (408 MHz)
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* [31:0] Core clock counter: Counts on every core clock cycle
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*/
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static void tegra234_read_counters(struct tegra_cpu_ctr *c)
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{
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struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
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void __iomem *actmon_reg;
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u32 cpuid, clusterid;
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u64 val;
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data->soc->ops->get_cpu_cluster_id(c->cpu, &cpuid, &clusterid);
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actmon_reg = CORE_ACTMON_CNTR_REG(data, clusterid, cpuid);
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val = readq(actmon_reg);
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c->last_refclk_cnt = upper_32_bits(val);
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c->last_coreclk_cnt = lower_32_bits(val);
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udelay(US_DELAY);
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val = readq(actmon_reg);
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c->refclk_cnt = upper_32_bits(val);
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c->coreclk_cnt = lower_32_bits(val);
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}
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static struct tegra_cpufreq_ops tegra234_cpufreq_ops = {
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.read_counters = tegra234_read_counters,
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.get_cpu_cluster_id = tegra234_get_cpu_cluster_id,
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.get_cpu_ndiv = tegra234_get_cpu_ndiv,
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.set_cpu_ndiv = tegra234_set_cpu_ndiv,
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};
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const struct tegra_cpufreq_soc tegra234_cpufreq_soc = {
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.ops = &tegra234_cpufreq_ops,
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.actmon_cntr_base = 0x9000,
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.maxcpus_per_cluster = 4,
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};
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static void tegra194_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid)
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{
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u64 mpidr;
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smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true);
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if (cpuid)
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*cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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if (clusterid)
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*clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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}
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/*
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* Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
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* The register provides frequency feedback information to
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* determine the average actual frequency a core has run at over
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* a period of time.
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* [31:0] PLLP counter: Counts at fixed frequency (408 MHz)
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* [63:32] Core clock counter: counts on every core clock cycle
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* where the core is architecturally clocking
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*/
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static u64 read_freq_feedback(void)
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{
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u64 val = 0;
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asm volatile("mrs %0, s3_0_c15_c0_5" : "=r" (val) : );
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return val;
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}
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static inline u32 map_ndiv_to_freq(struct mrq_cpu_ndiv_limits_response
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*nltbl, u16 ndiv)
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{
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return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv);
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}
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static void tegra194_read_counters(struct tegra_cpu_ctr *c)
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{
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u64 val;
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val = read_freq_feedback();
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c->last_refclk_cnt = lower_32_bits(val);
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c->last_coreclk_cnt = upper_32_bits(val);
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udelay(US_DELAY);
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val = read_freq_feedback();
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c->refclk_cnt = lower_32_bits(val);
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c->coreclk_cnt = upper_32_bits(val);
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}
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static void tegra_read_counters(struct work_struct *work)
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{
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struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
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struct read_counters_work *read_counters_work;
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struct tegra_cpu_ctr *c;
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/*
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* ref_clk_counter(32 bit counter) runs on constant clk,
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* pll_p(408MHz).
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* It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter
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* = 10526880 usec = 10.527 sec to overflow
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*
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* Like wise core_clk_counter(32 bit counter) runs on core clock.
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* It's synchronized to crab_clk (cpu_crab_clk) which runs at
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* freq of cluster. Assuming max cluster clock ~2000MHz,
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* It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter
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* = ~2.147 sec to overflow
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*/
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read_counters_work = container_of(work, struct read_counters_work,
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work);
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c = &read_counters_work->c;
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data->soc->ops->read_counters(c);
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}
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/*
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* Return instantaneous cpu speed
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* Instantaneous freq is calculated as -
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* -Takes sample on every query of getting the freq.
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* - Read core and ref clock counters;
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* - Delay for X us
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* - Read above cycle counters again
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* - Calculates freq by subtracting current and previous counters
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* divided by the delay time or eqv. of ref_clk_counter in delta time
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* - Return Kcycles/second, freq in KHz
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*
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* delta time period = x sec
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* = delta ref_clk_counter / (408 * 10^6) sec
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* freq in Hz = cycles/sec
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* = (delta cycles / x sec
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* = (delta cycles * 408 * 10^6) / delta ref_clk_counter
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* in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter
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*
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* @cpu - logical cpu whose freq to be updated
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* Returns freq in KHz on success, 0 if cpu is offline
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*/
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static unsigned int tegra194_calculate_speed(u32 cpu)
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{
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struct read_counters_work read_counters_work;
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struct tegra_cpu_ctr c;
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u32 delta_refcnt;
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u32 delta_ccnt;
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u32 rate_mhz;
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/*
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* udelay() is required to reconstruct cpu frequency over an
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* observation window. Using workqueue to call udelay() with
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* interrupts enabled.
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*/
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read_counters_work.c.cpu = cpu;
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INIT_WORK_ONSTACK(&read_counters_work.work, tegra_read_counters);
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queue_work_on(cpu, read_counters_wq, &read_counters_work.work);
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flush_work(&read_counters_work.work);
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c = read_counters_work.c;
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if (c.coreclk_cnt < c.last_coreclk_cnt)
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delta_ccnt = c.coreclk_cnt + (MAX_CNT - c.last_coreclk_cnt);
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else
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delta_ccnt = c.coreclk_cnt - c.last_coreclk_cnt;
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if (!delta_ccnt)
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return 0;
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/* ref clock is 32 bits */
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if (c.refclk_cnt < c.last_refclk_cnt)
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delta_refcnt = c.refclk_cnt + (MAX_CNT - c.last_refclk_cnt);
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else
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delta_refcnt = c.refclk_cnt - c.last_refclk_cnt;
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if (!delta_refcnt) {
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pr_debug("cpufreq: %d is idle, delta_refcnt: 0\n", cpu);
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return 0;
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}
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rate_mhz = ((unsigned long)(delta_ccnt * REF_CLK_MHZ)) / delta_refcnt;
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return (rate_mhz * KHZ); /* in KHz */
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}
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static void tegra194_get_cpu_ndiv_sysreg(void *ndiv)
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{
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u64 ndiv_val;
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asm volatile("mrs %0, s3_0_c15_c0_4" : "=r" (ndiv_val) : );
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*(u64 *)ndiv = ndiv_val;
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}
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static int tegra194_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv)
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{
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int ret;
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ret = smp_call_function_single(cpu, tegra194_get_cpu_ndiv_sysreg, &ndiv, true);
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return ret;
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}
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static void tegra194_set_cpu_ndiv_sysreg(void *data)
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{
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u64 ndiv_val = *(u64 *)data;
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asm volatile("msr s3_0_c15_c0_4, %0" : : "r" (ndiv_val));
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}
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static void tegra194_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv)
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{
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on_each_cpu_mask(policy->cpus, tegra194_set_cpu_ndiv_sysreg, &ndiv, true);
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}
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static unsigned int tegra194_get_speed(u32 cpu)
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{
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struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
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struct cpufreq_frequency_table *pos;
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u32 cpuid, clusterid;
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unsigned int rate;
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u64 ndiv;
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int ret;
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data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid);
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/* reconstruct actual cpu freq using counters */
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rate = tegra194_calculate_speed(cpu);
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/* get last written ndiv value */
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ret = data->soc->ops->get_cpu_ndiv(cpu, cpuid, clusterid, &ndiv);
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if (WARN_ON_ONCE(ret))
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return rate;
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/*
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* If the reconstructed frequency has acceptable delta from
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* the last written value, then return freq corresponding
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* to the last written ndiv value from freq_table. This is
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* done to return consistent value.
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*/
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cpufreq_for_each_valid_entry(pos, data->tables[clusterid]) {
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if (pos->driver_data != ndiv)
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continue;
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if (abs(pos->frequency - rate) > 115200) {
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pr_warn("cpufreq: cpu%d,cur:%u,set:%u,set ndiv:%llu\n",
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cpu, rate, pos->frequency, ndiv);
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} else {
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rate = pos->frequency;
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}
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break;
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}
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return rate;
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}
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static int tegra194_cpufreq_init(struct cpufreq_policy *policy)
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{
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struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
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int maxcpus_per_cluster = data->soc->maxcpus_per_cluster;
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u32 start_cpu, cpu;
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u32 clusterid;
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data->soc->ops->get_cpu_cluster_id(policy->cpu, NULL, &clusterid);
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if (clusterid >= data->num_clusters || !data->tables[clusterid])
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return -EINVAL;
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start_cpu = rounddown(policy->cpu, maxcpus_per_cluster);
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/* set same policy for all cpus in a cluster */
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for (cpu = start_cpu; cpu < (start_cpu + maxcpus_per_cluster); cpu++) {
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if (cpu_possible(cpu))
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cpumask_set_cpu(cpu, policy->cpus);
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}
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policy->freq_table = data->tables[clusterid];
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policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY;
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return 0;
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}
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static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct cpufreq_frequency_table *tbl = policy->freq_table + index;
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struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
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/*
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* Each core writes frequency in per core register. Then both cores
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* in a cluster run at same frequency which is the maximum frequency
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* request out of the values requested by both cores in that cluster.
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*/
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data->soc->ops->set_cpu_ndiv(policy, (u64)tbl->driver_data);
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return 0;
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}
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static struct cpufreq_driver tegra194_cpufreq_driver = {
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.name = "tegra194",
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.flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = tegra194_cpufreq_set_target,
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.get = tegra194_get_speed,
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.init = tegra194_cpufreq_init,
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.attr = cpufreq_generic_attr,
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};
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static struct tegra_cpufreq_ops tegra194_cpufreq_ops = {
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.read_counters = tegra194_read_counters,
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.get_cpu_cluster_id = tegra194_get_cpu_cluster_id,
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.get_cpu_ndiv = tegra194_get_cpu_ndiv,
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.set_cpu_ndiv = tegra194_set_cpu_ndiv,
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};
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const struct tegra_cpufreq_soc tegra194_cpufreq_soc = {
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.ops = &tegra194_cpufreq_ops,
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.maxcpus_per_cluster = 2,
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};
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static void tegra194_cpufreq_free_resources(void)
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{
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destroy_workqueue(read_counters_wq);
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}
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static struct cpufreq_frequency_table *
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init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp,
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unsigned int cluster_id)
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{
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struct cpufreq_frequency_table *freq_table;
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struct mrq_cpu_ndiv_limits_response resp;
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unsigned int num_freqs, ndiv, delta_ndiv;
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struct mrq_cpu_ndiv_limits_request req;
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struct tegra_bpmp_message msg;
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u16 freq_table_step_size;
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int err, index;
|
|
|
|
memset(&req, 0, sizeof(req));
|
|
req.cluster_id = cluster_id;
|
|
|
|
memset(&msg, 0, sizeof(msg));
|
|
msg.mrq = MRQ_CPU_NDIV_LIMITS;
|
|
msg.tx.data = &req;
|
|
msg.tx.size = sizeof(req);
|
|
msg.rx.data = &resp;
|
|
msg.rx.size = sizeof(resp);
|
|
|
|
err = tegra_bpmp_transfer(bpmp, &msg);
|
|
if (err)
|
|
return ERR_PTR(err);
|
|
if (msg.rx.ret == -BPMP_EINVAL) {
|
|
/* Cluster not available */
|
|
return NULL;
|
|
}
|
|
if (msg.rx.ret)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
/*
|
|
* Make sure frequency table step is a multiple of mdiv to match
|
|
* vhint table granularity.
|
|
*/
|
|
freq_table_step_size = resp.mdiv *
|
|
DIV_ROUND_UP(CPUFREQ_TBL_STEP_HZ, resp.ref_clk_hz);
|
|
|
|
dev_dbg(&pdev->dev, "cluster %d: frequency table step size: %d\n",
|
|
cluster_id, freq_table_step_size);
|
|
|
|
delta_ndiv = resp.ndiv_max - resp.ndiv_min;
|
|
|
|
if (unlikely(delta_ndiv == 0)) {
|
|
num_freqs = 1;
|
|
} else {
|
|
/* We store both ndiv_min and ndiv_max hence the +1 */
|
|
num_freqs = delta_ndiv / freq_table_step_size + 1;
|
|
}
|
|
|
|
num_freqs += (delta_ndiv % freq_table_step_size) ? 1 : 0;
|
|
|
|
freq_table = devm_kcalloc(&pdev->dev, num_freqs + 1,
|
|
sizeof(*freq_table), GFP_KERNEL);
|
|
if (!freq_table)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
for (index = 0, ndiv = resp.ndiv_min;
|
|
ndiv < resp.ndiv_max;
|
|
index++, ndiv += freq_table_step_size) {
|
|
freq_table[index].driver_data = ndiv;
|
|
freq_table[index].frequency = map_ndiv_to_freq(&resp, ndiv);
|
|
}
|
|
|
|
freq_table[index].driver_data = resp.ndiv_max;
|
|
freq_table[index++].frequency = map_ndiv_to_freq(&resp, resp.ndiv_max);
|
|
freq_table[index].frequency = CPUFREQ_TABLE_END;
|
|
|
|
return freq_table;
|
|
}
|
|
|
|
static int tegra194_cpufreq_probe(struct platform_device *pdev)
|
|
{
|
|
const struct tegra_cpufreq_soc *soc;
|
|
struct tegra194_cpufreq_data *data;
|
|
struct tegra_bpmp *bpmp;
|
|
int err, i;
|
|
|
|
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
soc = of_device_get_match_data(&pdev->dev);
|
|
|
|
if (soc->ops && soc->maxcpus_per_cluster) {
|
|
data->soc = soc;
|
|
} else {
|
|
dev_err(&pdev->dev, "soc data missing\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
data->num_clusters = MAX_CLUSTERS;
|
|
data->tables = devm_kcalloc(&pdev->dev, data->num_clusters,
|
|
sizeof(*data->tables), GFP_KERNEL);
|
|
if (!data->tables)
|
|
return -ENOMEM;
|
|
|
|
if (soc->actmon_cntr_base) {
|
|
/* mmio registers are used for frequency request and re-construction */
|
|
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(data->regs))
|
|
return PTR_ERR(data->regs);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
bpmp = tegra_bpmp_get(&pdev->dev);
|
|
if (IS_ERR(bpmp))
|
|
return PTR_ERR(bpmp);
|
|
|
|
read_counters_wq = alloc_workqueue("read_counters_wq", __WQ_LEGACY, 1);
|
|
if (!read_counters_wq) {
|
|
dev_err(&pdev->dev, "fail to create_workqueue\n");
|
|
err = -EINVAL;
|
|
goto put_bpmp;
|
|
}
|
|
|
|
for (i = 0; i < data->num_clusters; i++) {
|
|
data->tables[i] = init_freq_table(pdev, bpmp, i);
|
|
if (IS_ERR(data->tables[i])) {
|
|
err = PTR_ERR(data->tables[i]);
|
|
goto err_free_res;
|
|
}
|
|
}
|
|
|
|
tegra194_cpufreq_driver.driver_data = data;
|
|
|
|
err = cpufreq_register_driver(&tegra194_cpufreq_driver);
|
|
if (!err)
|
|
goto put_bpmp;
|
|
|
|
err_free_res:
|
|
tegra194_cpufreq_free_resources();
|
|
put_bpmp:
|
|
tegra_bpmp_put(bpmp);
|
|
return err;
|
|
}
|
|
|
|
static int tegra194_cpufreq_remove(struct platform_device *pdev)
|
|
{
|
|
cpufreq_unregister_driver(&tegra194_cpufreq_driver);
|
|
tegra194_cpufreq_free_resources();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id tegra194_cpufreq_of_match[] = {
|
|
{ .compatible = "nvidia,tegra194-ccplex", .data = &tegra194_cpufreq_soc },
|
|
{ .compatible = "nvidia,tegra234-ccplex-cluster", .data = &tegra234_cpufreq_soc },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static struct platform_driver tegra194_ccplex_driver = {
|
|
.driver = {
|
|
.name = "tegra194-cpufreq",
|
|
.of_match_table = tegra194_cpufreq_of_match,
|
|
},
|
|
.probe = tegra194_cpufreq_probe,
|
|
.remove = tegra194_cpufreq_remove,
|
|
};
|
|
module_platform_driver(tegra194_ccplex_driver);
|
|
|
|
MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
|
|
MODULE_AUTHOR("Sumit Gupta <sumitg@nvidia.com>");
|
|
MODULE_DESCRIPTION("NVIDIA Tegra194 cpufreq driver");
|
|
MODULE_LICENSE("GPL v2");
|