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The CXL specification claims S3 support at a hardware level, but at a system software level there are some missing pieces. Section 9.4 (CXL 2.0) rightly claims that "CXL mem adapters may need aux power to retain memory context across S3", but there is no enumeration mechanism for the OS to determine if a given adapter has that support. Moreover the save state and resume image for the system may inadvertantly end up in a CXL device that needs to be restored before the save state is recoverable. I.e. a circular dependency that is not resolvable without a third party save-area. Arrange for the cxl_mem driver to fail S3 attempts. This still nominaly allows for suspend, but requires unbinding all CXL memory devices before the suspend to ensure the typical DRAM flow is taken. The cxl_mem unbind flow is intended to also tear down all CXL memory regions associated with a given cxl_memdev. It is reasonable to assume that any device participating in a System RAM range published in the EFI memory map is covered by aux power and save-area outside the device itself. So this restriction can be minimized in the future once pre-existing region enumeration support arrives, and perhaps a spec update to clarify if the EFI memory map is sufficent for determining the range of devices managed by platform-firmware for S3 support. Per Rafael, if the CXL configuration prevents suspend then it should fail early before tasks are frozen, and mem_sleep should stop showing 'mem' as an option [1]. Effectively CXL augments the platform suspend ->valid() op since, for example, the ACPI ops are not aware of the CXL / PCI dependencies. Given the split role of platform firmware vs OS provisioned CXL memory it is up to the cxl_mem driver to determine if the CXL configuration has elements that platform firmware may not be prepared to restore. Link: https://lore.kernel.org/r/CAJZ5v0hGVN_=3iU8OLpHY3Ak35T5+JcBM-qs8SbojKrpd0VXsA@mail.gmail.com [1] Cc: "Rafael J. Wysocki" <rafael@kernel.org> Cc: Pavel Machek <pavel@ucw.cz> Cc: Len Brown <len.brown@intel.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://lore.kernel.org/r/165066828317.3907920.5690432272182042556.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
105 lines
3.9 KiB
Text
105 lines
3.9 KiB
Text
# SPDX-License-Identifier: GPL-2.0-only
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menuconfig CXL_BUS
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tristate "CXL (Compute Express Link) Devices Support"
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depends on PCI
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help
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CXL is a bus that is electrically compatible with PCI Express, but
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layers three protocols on that signalling (CXL.io, CXL.cache, and
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CXL.mem). The CXL.cache protocol allows devices to hold cachelines
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locally, the CXL.mem protocol allows devices to be fully coherent
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memory targets, the CXL.io protocol is equivalent to PCI Express.
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Say 'y' to enable support for the configuration and management of
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devices supporting these protocols.
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if CXL_BUS
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config CXL_PCI
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tristate "PCI manageability"
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default CXL_BUS
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help
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The CXL specification defines a "CXL memory device" sub-class in the
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PCI "memory controller" base class of devices. Device's identified by
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this class code provide support for volatile and / or persistent
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memory to be mapped into the system address map (Host-managed Device
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Memory (HDM)).
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Say 'y/m' to enable a driver that will attach to CXL memory expander
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devices enumerated by the memory device class code for configuration
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and management primarily via the mailbox interface. See Chapter 2.3
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Type 3 CXL Device in the CXL 2.0 specification for more details.
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If unsure say 'm'.
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config CXL_MEM_RAW_COMMANDS
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bool "RAW Command Interface for Memory Devices"
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depends on CXL_PCI
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help
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Enable CXL RAW command interface.
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The CXL driver ioctl interface may assign a kernel ioctl command
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number for each specification defined opcode. At any given point in
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time the number of opcodes that the specification defines and a device
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may implement may exceed the kernel's set of associated ioctl function
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numbers. The mismatch is either by omission, specification is too new,
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or by design. When prototyping new hardware, or developing / debugging
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the driver it is useful to be able to submit any possible command to
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the hardware, even commands that may crash the kernel due to their
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potential impact to memory currently in use by the kernel.
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If developing CXL hardware or the driver say Y, otherwise say N.
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config CXL_ACPI
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tristate "CXL ACPI: Platform Support"
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depends on ACPI
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default CXL_BUS
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select ACPI_TABLE_LIB
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help
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Enable support for host managed device memory (HDM) resources
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published by a platform's ACPI CXL memory layout description. See
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Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
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specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
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(https://www.computeexpresslink.org/spec-landing). The CXL core
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consumes these resource to publish the root of a cxl_port decode
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hierarchy to map regions that represent System RAM, or Persistent
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Memory regions to be managed by LIBNVDIMM.
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If unsure say 'm'.
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config CXL_PMEM
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tristate "CXL PMEM: Persistent Memory Support"
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depends on LIBNVDIMM
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default CXL_BUS
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help
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In addition to typical memory resources a platform may also advertise
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support for persistent memory attached via CXL. This support is
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managed via a bridge driver from CXL to the LIBNVDIMM system
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subsystem. Say 'y/m' to enable support for enumerating and
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provisioning the persistent memory capacity of CXL memory expanders.
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If unsure say 'm'.
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config CXL_MEM
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tristate "CXL: Memory Expansion"
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depends on CXL_PCI
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default CXL_BUS
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help
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The CXL.mem protocol allows a device to act as a provider of "System
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RAM" and/or "Persistent Memory" that is fully coherent as if the
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memory were attached to the typical CPU memory controller. This is
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known as HDM "Host-managed Device Memory".
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Say 'y/m' to enable a driver that will attach to CXL.mem devices for
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memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
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specification for a detailed description of HDM.
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If unsure say 'm'.
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config CXL_PORT
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default CXL_BUS
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tristate
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config CXL_SUSPEND
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def_bool y
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depends on SUSPEND && CXL_MEM
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endif
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