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![Lad Prabhakar](/assets/img/avatar_default.png)
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq_optional(). There are no non-DT users for this driver so interrupt range (irq_res->start-irq_res->end) is no longer required and with DT we will be sure it will be a single IRQ resource for each index. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220404155557.27316-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
1530 lines
40 KiB
C
1530 lines
40 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
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* Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/dma/nbpfaxi.h>
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#include "dmaengine.h"
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#define NBPF_REG_CHAN_OFFSET 0
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#define NBPF_REG_CHAN_SIZE 0x40
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/* Channel Current Transaction Byte register */
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#define NBPF_CHAN_CUR_TR_BYTE 0x20
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/* Channel Status register */
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#define NBPF_CHAN_STAT 0x24
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#define NBPF_CHAN_STAT_EN 1
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#define NBPF_CHAN_STAT_TACT 4
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#define NBPF_CHAN_STAT_ERR 0x10
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#define NBPF_CHAN_STAT_END 0x20
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#define NBPF_CHAN_STAT_TC 0x40
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#define NBPF_CHAN_STAT_DER 0x400
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/* Channel Control register */
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#define NBPF_CHAN_CTRL 0x28
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#define NBPF_CHAN_CTRL_SETEN 1
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#define NBPF_CHAN_CTRL_CLREN 2
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#define NBPF_CHAN_CTRL_STG 4
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#define NBPF_CHAN_CTRL_SWRST 8
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#define NBPF_CHAN_CTRL_CLRRQ 0x10
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#define NBPF_CHAN_CTRL_CLREND 0x20
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#define NBPF_CHAN_CTRL_CLRTC 0x40
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#define NBPF_CHAN_CTRL_SETSUS 0x100
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#define NBPF_CHAN_CTRL_CLRSUS 0x200
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/* Channel Configuration register */
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#define NBPF_CHAN_CFG 0x2c
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#define NBPF_CHAN_CFG_SEL 7 /* terminal SELect: 0..7 */
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#define NBPF_CHAN_CFG_REQD 8 /* REQuest Direction: DMAREQ is 0: input, 1: output */
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#define NBPF_CHAN_CFG_LOEN 0x10 /* LOw ENable: low DMA request line is: 0: inactive, 1: active */
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#define NBPF_CHAN_CFG_HIEN 0x20 /* HIgh ENable: high DMA request line is: 0: inactive, 1: active */
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#define NBPF_CHAN_CFG_LVL 0x40 /* LeVeL: DMA request line is sensed as 0: edge, 1: level */
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#define NBPF_CHAN_CFG_AM 0x700 /* ACK Mode: 0: Pulse mode, 1: Level mode, b'1x: Bus Cycle */
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#define NBPF_CHAN_CFG_SDS 0xf000 /* Source Data Size: 0: 8 bits,... , 7: 1024 bits */
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#define NBPF_CHAN_CFG_DDS 0xf0000 /* Destination Data Size: as above */
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#define NBPF_CHAN_CFG_SAD 0x100000 /* Source ADdress counting: 0: increment, 1: fixed */
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#define NBPF_CHAN_CFG_DAD 0x200000 /* Destination ADdress counting: 0: increment, 1: fixed */
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#define NBPF_CHAN_CFG_TM 0x400000 /* Transfer Mode: 0: single, 1: block TM */
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#define NBPF_CHAN_CFG_DEM 0x1000000 /* DMAEND interrupt Mask */
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#define NBPF_CHAN_CFG_TCM 0x2000000 /* DMATCO interrupt Mask */
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#define NBPF_CHAN_CFG_SBE 0x8000000 /* Sweep Buffer Enable */
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#define NBPF_CHAN_CFG_RSEL 0x10000000 /* RM: Register Set sELect */
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#define NBPF_CHAN_CFG_RSW 0x20000000 /* RM: Register Select sWitch */
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#define NBPF_CHAN_CFG_REN 0x40000000 /* RM: Register Set Enable */
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#define NBPF_CHAN_CFG_DMS 0x80000000 /* 0: register mode (RM), 1: link mode (LM) */
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#define NBPF_CHAN_NXLA 0x38
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#define NBPF_CHAN_CRLA 0x3c
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/* Link Header field */
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#define NBPF_HEADER_LV 1
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#define NBPF_HEADER_LE 2
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#define NBPF_HEADER_WBD 4
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#define NBPF_HEADER_DIM 8
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#define NBPF_CTRL 0x300
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#define NBPF_CTRL_PR 1 /* 0: fixed priority, 1: round robin */
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#define NBPF_CTRL_LVINT 2 /* DMAEND and DMAERR signalling: 0: pulse, 1: level */
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#define NBPF_DSTAT_ER 0x314
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#define NBPF_DSTAT_END 0x318
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#define NBPF_DMA_BUSWIDTHS \
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(BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
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BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
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struct nbpf_config {
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int num_channels;
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int buffer_size;
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};
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/*
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* We've got 3 types of objects, used to describe DMA transfers:
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* 1. high-level descriptor, containing a struct dma_async_tx_descriptor object
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* in it, used to communicate with the user
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* 2. hardware DMA link descriptors, that we pass to DMAC for DMA transfer
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* queuing, these must be DMAable, using either the streaming DMA API or
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* allocated from coherent memory - one per SG segment
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* 3. one per SG segment descriptors, used to manage HW link descriptors from
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* (2). They do not have to be DMAable. They can either be (a) allocated
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* together with link descriptors as mixed (DMA / CPU) objects, or (b)
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* separately. Even if allocated separately it would be best to link them
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* to link descriptors once during channel resource allocation and always
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* use them as a single object.
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* Therefore for both cases (a) and (b) at run-time objects (2) and (3) shall be
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* treated as a single SG segment descriptor.
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*/
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struct nbpf_link_reg {
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u32 header;
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u32 src_addr;
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u32 dst_addr;
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u32 transaction_size;
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u32 config;
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u32 interval;
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u32 extension;
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u32 next;
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} __packed;
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struct nbpf_device;
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struct nbpf_channel;
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struct nbpf_desc;
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struct nbpf_link_desc {
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struct nbpf_link_reg *hwdesc;
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dma_addr_t hwdesc_dma_addr;
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struct nbpf_desc *desc;
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struct list_head node;
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};
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/**
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* struct nbpf_desc - DMA transfer descriptor
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* @async_tx: dmaengine object
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* @user_wait: waiting for a user ack
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* @length: total transfer length
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* @chan: associated DMAC channel
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* @sg: list of hardware descriptors, represented by struct nbpf_link_desc
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* @node: member in channel descriptor lists
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*/
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struct nbpf_desc {
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struct dma_async_tx_descriptor async_tx;
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bool user_wait;
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size_t length;
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struct nbpf_channel *chan;
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struct list_head sg;
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struct list_head node;
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};
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/* Take a wild guess: allocate 4 segments per descriptor */
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#define NBPF_SEGMENTS_PER_DESC 4
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#define NBPF_DESCS_PER_PAGE ((PAGE_SIZE - sizeof(struct list_head)) / \
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(sizeof(struct nbpf_desc) + \
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NBPF_SEGMENTS_PER_DESC * \
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(sizeof(struct nbpf_link_desc) + sizeof(struct nbpf_link_reg))))
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#define NBPF_SEGMENTS_PER_PAGE (NBPF_SEGMENTS_PER_DESC * NBPF_DESCS_PER_PAGE)
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struct nbpf_desc_page {
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struct list_head node;
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struct nbpf_desc desc[NBPF_DESCS_PER_PAGE];
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struct nbpf_link_desc ldesc[NBPF_SEGMENTS_PER_PAGE];
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struct nbpf_link_reg hwdesc[NBPF_SEGMENTS_PER_PAGE];
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};
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/**
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* struct nbpf_channel - one DMAC channel
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* @dma_chan: standard dmaengine channel object
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* @tasklet: channel specific tasklet used for callbacks
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* @base: register address base
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* @nbpf: DMAC
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* @name: IRQ name
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* @irq: IRQ number
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* @slave_src_addr: source address for slave DMA
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* @slave_src_width: source slave data size in bytes
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* @slave_src_burst: maximum source slave burst size in bytes
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* @slave_dst_addr: destination address for slave DMA
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* @slave_dst_width: destination slave data size in bytes
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* @slave_dst_burst: maximum destination slave burst size in bytes
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* @terminal: DMA terminal, assigned to this channel
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* @dmarq_cfg: DMA request line configuration - high / low, edge / level for NBPF_CHAN_CFG
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* @flags: configuration flags from DT
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* @lock: protect descriptor lists
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* @free_links: list of free link descriptors
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* @free: list of free descriptors
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* @queued: list of queued descriptors
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* @active: list of descriptors, scheduled for processing
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* @done: list of completed descriptors, waiting post-processing
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* @desc_page: list of additionally allocated descriptor pages - if any
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* @running: linked descriptor of running transaction
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* @paused: are translations on this channel paused?
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*/
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struct nbpf_channel {
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struct dma_chan dma_chan;
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struct tasklet_struct tasklet;
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void __iomem *base;
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struct nbpf_device *nbpf;
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char name[16];
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int irq;
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dma_addr_t slave_src_addr;
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size_t slave_src_width;
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size_t slave_src_burst;
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dma_addr_t slave_dst_addr;
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size_t slave_dst_width;
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size_t slave_dst_burst;
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unsigned int terminal;
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u32 dmarq_cfg;
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unsigned long flags;
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spinlock_t lock;
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struct list_head free_links;
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struct list_head free;
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struct list_head queued;
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struct list_head active;
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struct list_head done;
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struct list_head desc_page;
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struct nbpf_desc *running;
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bool paused;
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};
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struct nbpf_device {
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struct dma_device dma_dev;
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void __iomem *base;
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u32 max_burst_mem_read;
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u32 max_burst_mem_write;
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struct clk *clk;
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const struct nbpf_config *config;
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unsigned int eirq;
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struct nbpf_channel chan[];
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};
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enum nbpf_model {
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NBPF1B4,
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NBPF1B8,
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NBPF1B16,
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NBPF4B4,
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NBPF4B8,
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NBPF4B16,
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NBPF8B4,
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NBPF8B8,
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NBPF8B16,
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};
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static struct nbpf_config nbpf_cfg[] = {
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[NBPF1B4] = {
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.num_channels = 1,
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.buffer_size = 4,
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},
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[NBPF1B8] = {
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.num_channels = 1,
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.buffer_size = 8,
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},
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[NBPF1B16] = {
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.num_channels = 1,
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.buffer_size = 16,
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},
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[NBPF4B4] = {
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.num_channels = 4,
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.buffer_size = 4,
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},
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[NBPF4B8] = {
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.num_channels = 4,
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.buffer_size = 8,
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},
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[NBPF4B16] = {
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.num_channels = 4,
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.buffer_size = 16,
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},
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[NBPF8B4] = {
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.num_channels = 8,
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.buffer_size = 4,
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},
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[NBPF8B8] = {
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.num_channels = 8,
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.buffer_size = 8,
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},
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[NBPF8B16] = {
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.num_channels = 8,
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.buffer_size = 16,
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},
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};
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#define nbpf_to_chan(d) container_of(d, struct nbpf_channel, dma_chan)
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/*
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* dmaengine drivers seem to have a lot in common and instead of sharing more
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* code, they reimplement those common algorithms independently. In this driver
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* we try to separate the hardware-specific part from the (largely) generic
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* part. This improves code readability and makes it possible in the future to
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* reuse the generic code in form of a helper library. That generic code should
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* be suitable for various DMA controllers, using transfer descriptors in RAM
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* and pushing one SG list at a time to the DMA controller.
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*/
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/* Hardware-specific part */
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static inline u32 nbpf_chan_read(struct nbpf_channel *chan,
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unsigned int offset)
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{
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u32 data = ioread32(chan->base + offset);
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dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
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__func__, chan->base, offset, data);
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return data;
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}
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static inline void nbpf_chan_write(struct nbpf_channel *chan,
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unsigned int offset, u32 data)
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{
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iowrite32(data, chan->base + offset);
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dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n",
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__func__, chan->base, offset, data);
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}
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static inline u32 nbpf_read(struct nbpf_device *nbpf,
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unsigned int offset)
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{
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u32 data = ioread32(nbpf->base + offset);
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dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
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__func__, nbpf->base, offset, data);
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return data;
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}
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static inline void nbpf_write(struct nbpf_device *nbpf,
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unsigned int offset, u32 data)
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{
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iowrite32(data, nbpf->base + offset);
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dev_dbg(nbpf->dma_dev.dev, "%s(0x%p + 0x%x) = 0x%x\n",
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__func__, nbpf->base, offset, data);
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}
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static void nbpf_chan_halt(struct nbpf_channel *chan)
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{
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nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
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}
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static bool nbpf_status_get(struct nbpf_channel *chan)
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{
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u32 status = nbpf_read(chan->nbpf, NBPF_DSTAT_END);
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return status & BIT(chan - chan->nbpf->chan);
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}
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static void nbpf_status_ack(struct nbpf_channel *chan)
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{
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nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREND);
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}
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static u32 nbpf_error_get(struct nbpf_device *nbpf)
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{
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return nbpf_read(nbpf, NBPF_DSTAT_ER);
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}
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static struct nbpf_channel *nbpf_error_get_channel(struct nbpf_device *nbpf, u32 error)
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{
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return nbpf->chan + __ffs(error);
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}
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static void nbpf_error_clear(struct nbpf_channel *chan)
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{
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u32 status;
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int i;
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/* Stop the channel, make sure DMA has been aborted */
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nbpf_chan_halt(chan);
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for (i = 1000; i; i--) {
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status = nbpf_chan_read(chan, NBPF_CHAN_STAT);
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if (!(status & NBPF_CHAN_STAT_TACT))
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break;
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cpu_relax();
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}
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if (!i)
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dev_err(chan->dma_chan.device->dev,
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"%s(): abort timeout, channel status 0x%x\n", __func__, status);
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nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SWRST);
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}
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static int nbpf_start(struct nbpf_desc *desc)
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{
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struct nbpf_channel *chan = desc->chan;
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struct nbpf_link_desc *ldesc = list_first_entry(&desc->sg, struct nbpf_link_desc, node);
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nbpf_chan_write(chan, NBPF_CHAN_NXLA, (u32)ldesc->hwdesc_dma_addr);
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nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETEN | NBPF_CHAN_CTRL_CLRSUS);
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chan->paused = false;
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/* Software trigger MEMCPY - only MEMCPY uses the block mode */
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if (ldesc->hwdesc->config & NBPF_CHAN_CFG_TM)
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nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_STG);
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dev_dbg(chan->nbpf->dma_dev.dev, "%s(): next 0x%x, cur 0x%x\n", __func__,
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nbpf_chan_read(chan, NBPF_CHAN_NXLA), nbpf_chan_read(chan, NBPF_CHAN_CRLA));
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return 0;
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}
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static void nbpf_chan_prepare(struct nbpf_channel *chan)
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{
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chan->dmarq_cfg = (chan->flags & NBPF_SLAVE_RQ_HIGH ? NBPF_CHAN_CFG_HIEN : 0) |
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(chan->flags & NBPF_SLAVE_RQ_LOW ? NBPF_CHAN_CFG_LOEN : 0) |
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(chan->flags & NBPF_SLAVE_RQ_LEVEL ?
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NBPF_CHAN_CFG_LVL | (NBPF_CHAN_CFG_AM & 0x200) : 0) |
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chan->terminal;
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}
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static void nbpf_chan_prepare_default(struct nbpf_channel *chan)
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{
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/* Don't output DMAACK */
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chan->dmarq_cfg = NBPF_CHAN_CFG_AM & 0x400;
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chan->terminal = 0;
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chan->flags = 0;
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}
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static void nbpf_chan_configure(struct nbpf_channel *chan)
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{
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/*
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* We assume, that only the link mode and DMA request line configuration
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* have to be set in the configuration register manually. Dynamic
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* per-transfer configuration will be loaded from transfer descriptors.
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*/
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nbpf_chan_write(chan, NBPF_CHAN_CFG, NBPF_CHAN_CFG_DMS | chan->dmarq_cfg);
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}
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static u32 nbpf_xfer_ds(struct nbpf_device *nbpf, size_t size,
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enum dma_transfer_direction direction)
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{
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int max_burst = nbpf->config->buffer_size * 8;
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|
|
if (nbpf->max_burst_mem_read || nbpf->max_burst_mem_write) {
|
|
switch (direction) {
|
|
case DMA_MEM_TO_MEM:
|
|
max_burst = min_not_zero(nbpf->max_burst_mem_read,
|
|
nbpf->max_burst_mem_write);
|
|
break;
|
|
case DMA_MEM_TO_DEV:
|
|
if (nbpf->max_burst_mem_read)
|
|
max_burst = nbpf->max_burst_mem_read;
|
|
break;
|
|
case DMA_DEV_TO_MEM:
|
|
if (nbpf->max_burst_mem_write)
|
|
max_burst = nbpf->max_burst_mem_write;
|
|
break;
|
|
case DMA_DEV_TO_DEV:
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Maximum supported bursts depend on the buffer size */
|
|
return min_t(int, __ffs(size), ilog2(max_burst));
|
|
}
|
|
|
|
static size_t nbpf_xfer_size(struct nbpf_device *nbpf,
|
|
enum dma_slave_buswidth width, u32 burst)
|
|
{
|
|
size_t size;
|
|
|
|
if (!burst)
|
|
burst = 1;
|
|
|
|
switch (width) {
|
|
case DMA_SLAVE_BUSWIDTH_8_BYTES:
|
|
size = 8 * burst;
|
|
break;
|
|
|
|
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
|
size = 4 * burst;
|
|
break;
|
|
|
|
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
|
size = 2 * burst;
|
|
break;
|
|
|
|
default:
|
|
pr_warn("%s(): invalid bus width %u\n", __func__, width);
|
|
fallthrough;
|
|
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
|
size = burst;
|
|
}
|
|
|
|
return nbpf_xfer_ds(nbpf, size, DMA_TRANS_NONE);
|
|
}
|
|
|
|
/*
|
|
* We need a way to recognise slaves, whose data is sent "raw" over the bus,
|
|
* i.e. it isn't known in advance how many bytes will be received. Therefore
|
|
* the slave driver has to provide a "large enough" buffer and either read the
|
|
* buffer, when it is full, or detect, that some data has arrived, then wait for
|
|
* a timeout, if no more data arrives - receive what's already there. We want to
|
|
* handle such slaves in a special way to allow an optimised mode for other
|
|
* users, for whom the amount of data is known in advance. So far there's no way
|
|
* to recognise such slaves. We use a data-width check to distinguish between
|
|
* the SD host and the PL011 UART.
|
|
*/
|
|
|
|
static int nbpf_prep_one(struct nbpf_link_desc *ldesc,
|
|
enum dma_transfer_direction direction,
|
|
dma_addr_t src, dma_addr_t dst, size_t size, bool last)
|
|
{
|
|
struct nbpf_link_reg *hwdesc = ldesc->hwdesc;
|
|
struct nbpf_desc *desc = ldesc->desc;
|
|
struct nbpf_channel *chan = desc->chan;
|
|
struct device *dev = chan->dma_chan.device->dev;
|
|
size_t mem_xfer, slave_xfer;
|
|
bool can_burst;
|
|
|
|
hwdesc->header = NBPF_HEADER_WBD | NBPF_HEADER_LV |
|
|
(last ? NBPF_HEADER_LE : 0);
|
|
|
|
hwdesc->src_addr = src;
|
|
hwdesc->dst_addr = dst;
|
|
hwdesc->transaction_size = size;
|
|
|
|
/*
|
|
* set config: SAD, DAD, DDS, SDS, etc.
|
|
* Note on transfer sizes: the DMAC can perform unaligned DMA transfers,
|
|
* but it is important to have transaction size a multiple of both
|
|
* receiver and transmitter transfer sizes. It is also possible to use
|
|
* different RAM and device transfer sizes, and it does work well with
|
|
* some devices, e.g. with V08R07S01E SD host controllers, which can use
|
|
* 128 byte transfers. But this doesn't work with other devices,
|
|
* especially when the transaction size is unknown. This is the case,
|
|
* e.g. with serial drivers like amba-pl011.c. For reception it sets up
|
|
* the transaction size of 4K and if fewer bytes are received, it
|
|
* pauses DMA and reads out data received via DMA as well as those left
|
|
* in the Rx FIFO. For this to work with the RAM side using burst
|
|
* transfers we enable the SBE bit and terminate the transfer in our
|
|
* .device_pause handler.
|
|
*/
|
|
mem_xfer = nbpf_xfer_ds(chan->nbpf, size, direction);
|
|
|
|
switch (direction) {
|
|
case DMA_DEV_TO_MEM:
|
|
can_burst = chan->slave_src_width >= 3;
|
|
slave_xfer = min(mem_xfer, can_burst ?
|
|
chan->slave_src_burst : chan->slave_src_width);
|
|
/*
|
|
* Is the slave narrower than 64 bits, i.e. isn't using the full
|
|
* bus width and cannot use bursts?
|
|
*/
|
|
if (mem_xfer > chan->slave_src_burst && !can_burst)
|
|
mem_xfer = chan->slave_src_burst;
|
|
/* Device-to-RAM DMA is unreliable without REQD set */
|
|
hwdesc->config = NBPF_CHAN_CFG_SAD | (NBPF_CHAN_CFG_DDS & (mem_xfer << 16)) |
|
|
(NBPF_CHAN_CFG_SDS & (slave_xfer << 12)) | NBPF_CHAN_CFG_REQD |
|
|
NBPF_CHAN_CFG_SBE;
|
|
break;
|
|
|
|
case DMA_MEM_TO_DEV:
|
|
slave_xfer = min(mem_xfer, chan->slave_dst_width >= 3 ?
|
|
chan->slave_dst_burst : chan->slave_dst_width);
|
|
hwdesc->config = NBPF_CHAN_CFG_DAD | (NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
|
|
(NBPF_CHAN_CFG_DDS & (slave_xfer << 16)) | NBPF_CHAN_CFG_REQD;
|
|
break;
|
|
|
|
case DMA_MEM_TO_MEM:
|
|
hwdesc->config = NBPF_CHAN_CFG_TCM | NBPF_CHAN_CFG_TM |
|
|
(NBPF_CHAN_CFG_SDS & (mem_xfer << 12)) |
|
|
(NBPF_CHAN_CFG_DDS & (mem_xfer << 16));
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
hwdesc->config |= chan->dmarq_cfg | (last ? 0 : NBPF_CHAN_CFG_DEM) |
|
|
NBPF_CHAN_CFG_DMS;
|
|
|
|
dev_dbg(dev, "%s(): desc @ %pad: hdr 0x%x, cfg 0x%x, %zu @ %pad -> %pad\n",
|
|
__func__, &ldesc->hwdesc_dma_addr, hwdesc->header,
|
|
hwdesc->config, size, &src, &dst);
|
|
|
|
dma_sync_single_for_device(dev, ldesc->hwdesc_dma_addr, sizeof(*hwdesc),
|
|
DMA_TO_DEVICE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static size_t nbpf_bytes_left(struct nbpf_channel *chan)
|
|
{
|
|
return nbpf_chan_read(chan, NBPF_CHAN_CUR_TR_BYTE);
|
|
}
|
|
|
|
static void nbpf_configure(struct nbpf_device *nbpf)
|
|
{
|
|
nbpf_write(nbpf, NBPF_CTRL, NBPF_CTRL_LVINT);
|
|
}
|
|
|
|
/* Generic part */
|
|
|
|
/* DMA ENGINE functions */
|
|
static void nbpf_issue_pending(struct dma_chan *dchan)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
unsigned long flags;
|
|
|
|
dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
|
|
|
|
spin_lock_irqsave(&chan->lock, flags);
|
|
if (list_empty(&chan->queued))
|
|
goto unlock;
|
|
|
|
list_splice_tail_init(&chan->queued, &chan->active);
|
|
|
|
if (!chan->running) {
|
|
struct nbpf_desc *desc = list_first_entry(&chan->active,
|
|
struct nbpf_desc, node);
|
|
if (!nbpf_start(desc))
|
|
chan->running = desc;
|
|
}
|
|
|
|
unlock:
|
|
spin_unlock_irqrestore(&chan->lock, flags);
|
|
}
|
|
|
|
static enum dma_status nbpf_tx_status(struct dma_chan *dchan,
|
|
dma_cookie_t cookie, struct dma_tx_state *state)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
enum dma_status status = dma_cookie_status(dchan, cookie, state);
|
|
|
|
if (state) {
|
|
dma_cookie_t running;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&chan->lock, flags);
|
|
running = chan->running ? chan->running->async_tx.cookie : -EINVAL;
|
|
|
|
if (cookie == running) {
|
|
state->residue = nbpf_bytes_left(chan);
|
|
dev_dbg(dchan->device->dev, "%s(): residue %u\n", __func__,
|
|
state->residue);
|
|
} else if (status == DMA_IN_PROGRESS) {
|
|
struct nbpf_desc *desc;
|
|
bool found = false;
|
|
|
|
list_for_each_entry(desc, &chan->active, node)
|
|
if (desc->async_tx.cookie == cookie) {
|
|
found = true;
|
|
break;
|
|
}
|
|
|
|
if (!found)
|
|
list_for_each_entry(desc, &chan->queued, node)
|
|
if (desc->async_tx.cookie == cookie) {
|
|
found = true;
|
|
break;
|
|
|
|
}
|
|
|
|
state->residue = found ? desc->length : 0;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&chan->lock, flags);
|
|
}
|
|
|
|
if (chan->paused)
|
|
status = DMA_PAUSED;
|
|
|
|
return status;
|
|
}
|
|
|
|
static dma_cookie_t nbpf_tx_submit(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
struct nbpf_desc *desc = container_of(tx, struct nbpf_desc, async_tx);
|
|
struct nbpf_channel *chan = desc->chan;
|
|
unsigned long flags;
|
|
dma_cookie_t cookie;
|
|
|
|
spin_lock_irqsave(&chan->lock, flags);
|
|
cookie = dma_cookie_assign(tx);
|
|
list_add_tail(&desc->node, &chan->queued);
|
|
spin_unlock_irqrestore(&chan->lock, flags);
|
|
|
|
dev_dbg(chan->dma_chan.device->dev, "Entry %s(%d)\n", __func__, cookie);
|
|
|
|
return cookie;
|
|
}
|
|
|
|
static int nbpf_desc_page_alloc(struct nbpf_channel *chan)
|
|
{
|
|
struct dma_chan *dchan = &chan->dma_chan;
|
|
struct nbpf_desc_page *dpage = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA);
|
|
struct nbpf_link_desc *ldesc;
|
|
struct nbpf_link_reg *hwdesc;
|
|
struct nbpf_desc *desc;
|
|
LIST_HEAD(head);
|
|
LIST_HEAD(lhead);
|
|
int i;
|
|
struct device *dev = dchan->device->dev;
|
|
|
|
if (!dpage)
|
|
return -ENOMEM;
|
|
|
|
dev_dbg(dev, "%s(): alloc %lu descriptors, %lu segments, total alloc %zu\n",
|
|
__func__, NBPF_DESCS_PER_PAGE, NBPF_SEGMENTS_PER_PAGE, sizeof(*dpage));
|
|
|
|
for (i = 0, ldesc = dpage->ldesc, hwdesc = dpage->hwdesc;
|
|
i < ARRAY_SIZE(dpage->ldesc);
|
|
i++, ldesc++, hwdesc++) {
|
|
ldesc->hwdesc = hwdesc;
|
|
list_add_tail(&ldesc->node, &lhead);
|
|
ldesc->hwdesc_dma_addr = dma_map_single(dchan->device->dev,
|
|
hwdesc, sizeof(*hwdesc), DMA_TO_DEVICE);
|
|
|
|
dev_dbg(dev, "%s(): mapped 0x%p to %pad\n", __func__,
|
|
hwdesc, &ldesc->hwdesc_dma_addr);
|
|
}
|
|
|
|
for (i = 0, desc = dpage->desc;
|
|
i < ARRAY_SIZE(dpage->desc);
|
|
i++, desc++) {
|
|
dma_async_tx_descriptor_init(&desc->async_tx, dchan);
|
|
desc->async_tx.tx_submit = nbpf_tx_submit;
|
|
desc->chan = chan;
|
|
INIT_LIST_HEAD(&desc->sg);
|
|
list_add_tail(&desc->node, &head);
|
|
}
|
|
|
|
/*
|
|
* This function cannot be called from interrupt context, so, no need to
|
|
* save flags
|
|
*/
|
|
spin_lock_irq(&chan->lock);
|
|
list_splice_tail(&lhead, &chan->free_links);
|
|
list_splice_tail(&head, &chan->free);
|
|
list_add(&dpage->node, &chan->desc_page);
|
|
spin_unlock_irq(&chan->lock);
|
|
|
|
return ARRAY_SIZE(dpage->desc);
|
|
}
|
|
|
|
static void nbpf_desc_put(struct nbpf_desc *desc)
|
|
{
|
|
struct nbpf_channel *chan = desc->chan;
|
|
struct nbpf_link_desc *ldesc, *tmp;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&chan->lock, flags);
|
|
list_for_each_entry_safe(ldesc, tmp, &desc->sg, node)
|
|
list_move(&ldesc->node, &chan->free_links);
|
|
|
|
list_add(&desc->node, &chan->free);
|
|
spin_unlock_irqrestore(&chan->lock, flags);
|
|
}
|
|
|
|
static void nbpf_scan_acked(struct nbpf_channel *chan)
|
|
{
|
|
struct nbpf_desc *desc, *tmp;
|
|
unsigned long flags;
|
|
LIST_HEAD(head);
|
|
|
|
spin_lock_irqsave(&chan->lock, flags);
|
|
list_for_each_entry_safe(desc, tmp, &chan->done, node)
|
|
if (async_tx_test_ack(&desc->async_tx) && desc->user_wait) {
|
|
list_move(&desc->node, &head);
|
|
desc->user_wait = false;
|
|
}
|
|
spin_unlock_irqrestore(&chan->lock, flags);
|
|
|
|
list_for_each_entry_safe(desc, tmp, &head, node) {
|
|
list_del(&desc->node);
|
|
nbpf_desc_put(desc);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* We have to allocate descriptors with the channel lock dropped. This means,
|
|
* before we re-acquire the lock buffers can be taken already, so we have to
|
|
* re-check after re-acquiring the lock and possibly retry, if buffers are gone
|
|
* again.
|
|
*/
|
|
static struct nbpf_desc *nbpf_desc_get(struct nbpf_channel *chan, size_t len)
|
|
{
|
|
struct nbpf_desc *desc = NULL;
|
|
struct nbpf_link_desc *ldesc, *prev = NULL;
|
|
|
|
nbpf_scan_acked(chan);
|
|
|
|
spin_lock_irq(&chan->lock);
|
|
|
|
do {
|
|
int i = 0, ret;
|
|
|
|
if (list_empty(&chan->free)) {
|
|
/* No more free descriptors */
|
|
spin_unlock_irq(&chan->lock);
|
|
ret = nbpf_desc_page_alloc(chan);
|
|
if (ret < 0)
|
|
return NULL;
|
|
spin_lock_irq(&chan->lock);
|
|
continue;
|
|
}
|
|
desc = list_first_entry(&chan->free, struct nbpf_desc, node);
|
|
list_del(&desc->node);
|
|
|
|
do {
|
|
if (list_empty(&chan->free_links)) {
|
|
/* No more free link descriptors */
|
|
spin_unlock_irq(&chan->lock);
|
|
ret = nbpf_desc_page_alloc(chan);
|
|
if (ret < 0) {
|
|
nbpf_desc_put(desc);
|
|
return NULL;
|
|
}
|
|
spin_lock_irq(&chan->lock);
|
|
continue;
|
|
}
|
|
|
|
ldesc = list_first_entry(&chan->free_links,
|
|
struct nbpf_link_desc, node);
|
|
ldesc->desc = desc;
|
|
if (prev)
|
|
prev->hwdesc->next = (u32)ldesc->hwdesc_dma_addr;
|
|
|
|
prev = ldesc;
|
|
list_move_tail(&ldesc->node, &desc->sg);
|
|
|
|
i++;
|
|
} while (i < len);
|
|
} while (!desc);
|
|
|
|
prev->hwdesc->next = 0;
|
|
|
|
spin_unlock_irq(&chan->lock);
|
|
|
|
return desc;
|
|
}
|
|
|
|
static void nbpf_chan_idle(struct nbpf_channel *chan)
|
|
{
|
|
struct nbpf_desc *desc, *tmp;
|
|
unsigned long flags;
|
|
LIST_HEAD(head);
|
|
|
|
spin_lock_irqsave(&chan->lock, flags);
|
|
|
|
list_splice_init(&chan->done, &head);
|
|
list_splice_init(&chan->active, &head);
|
|
list_splice_init(&chan->queued, &head);
|
|
|
|
chan->running = NULL;
|
|
|
|
spin_unlock_irqrestore(&chan->lock, flags);
|
|
|
|
list_for_each_entry_safe(desc, tmp, &head, node) {
|
|
dev_dbg(chan->nbpf->dma_dev.dev, "%s(): force-free desc %p cookie %d\n",
|
|
__func__, desc, desc->async_tx.cookie);
|
|
list_del(&desc->node);
|
|
nbpf_desc_put(desc);
|
|
}
|
|
}
|
|
|
|
static int nbpf_pause(struct dma_chan *dchan)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
|
|
dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
|
|
|
|
chan->paused = true;
|
|
nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_SETSUS);
|
|
/* See comment in nbpf_prep_one() */
|
|
nbpf_chan_write(chan, NBPF_CHAN_CTRL, NBPF_CHAN_CTRL_CLREN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nbpf_terminate_all(struct dma_chan *dchan)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
|
|
dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
|
|
dev_dbg(dchan->device->dev, "Terminating\n");
|
|
|
|
nbpf_chan_halt(chan);
|
|
nbpf_chan_idle(chan);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nbpf_config(struct dma_chan *dchan,
|
|
struct dma_slave_config *config)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
|
|
dev_dbg(dchan->device->dev, "Entry %s\n", __func__);
|
|
|
|
/*
|
|
* We could check config->slave_id to match chan->terminal here,
|
|
* but with DT they would be coming from the same source, so
|
|
* such a check would be superflous
|
|
*/
|
|
|
|
chan->slave_dst_addr = config->dst_addr;
|
|
chan->slave_dst_width = nbpf_xfer_size(chan->nbpf,
|
|
config->dst_addr_width, 1);
|
|
chan->slave_dst_burst = nbpf_xfer_size(chan->nbpf,
|
|
config->dst_addr_width,
|
|
config->dst_maxburst);
|
|
chan->slave_src_addr = config->src_addr;
|
|
chan->slave_src_width = nbpf_xfer_size(chan->nbpf,
|
|
config->src_addr_width, 1);
|
|
chan->slave_src_burst = nbpf_xfer_size(chan->nbpf,
|
|
config->src_addr_width,
|
|
config->src_maxburst);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *nbpf_prep_sg(struct nbpf_channel *chan,
|
|
struct scatterlist *src_sg, struct scatterlist *dst_sg,
|
|
size_t len, enum dma_transfer_direction direction,
|
|
unsigned long flags)
|
|
{
|
|
struct nbpf_link_desc *ldesc;
|
|
struct scatterlist *mem_sg;
|
|
struct nbpf_desc *desc;
|
|
bool inc_src, inc_dst;
|
|
size_t data_len = 0;
|
|
int i = 0;
|
|
|
|
switch (direction) {
|
|
case DMA_DEV_TO_MEM:
|
|
mem_sg = dst_sg;
|
|
inc_src = false;
|
|
inc_dst = true;
|
|
break;
|
|
|
|
case DMA_MEM_TO_DEV:
|
|
mem_sg = src_sg;
|
|
inc_src = true;
|
|
inc_dst = false;
|
|
break;
|
|
|
|
default:
|
|
case DMA_MEM_TO_MEM:
|
|
mem_sg = src_sg;
|
|
inc_src = true;
|
|
inc_dst = true;
|
|
}
|
|
|
|
desc = nbpf_desc_get(chan, len);
|
|
if (!desc)
|
|
return NULL;
|
|
|
|
desc->async_tx.flags = flags;
|
|
desc->async_tx.cookie = -EBUSY;
|
|
desc->user_wait = false;
|
|
|
|
/*
|
|
* This is a private descriptor list, and we own the descriptor. No need
|
|
* to lock.
|
|
*/
|
|
list_for_each_entry(ldesc, &desc->sg, node) {
|
|
int ret = nbpf_prep_one(ldesc, direction,
|
|
sg_dma_address(src_sg),
|
|
sg_dma_address(dst_sg),
|
|
sg_dma_len(mem_sg),
|
|
i == len - 1);
|
|
if (ret < 0) {
|
|
nbpf_desc_put(desc);
|
|
return NULL;
|
|
}
|
|
data_len += sg_dma_len(mem_sg);
|
|
if (inc_src)
|
|
src_sg = sg_next(src_sg);
|
|
if (inc_dst)
|
|
dst_sg = sg_next(dst_sg);
|
|
mem_sg = direction == DMA_DEV_TO_MEM ? dst_sg : src_sg;
|
|
i++;
|
|
}
|
|
|
|
desc->length = data_len;
|
|
|
|
/* The user has to return the descriptor to us ASAP via .tx_submit() */
|
|
return &desc->async_tx;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *nbpf_prep_memcpy(
|
|
struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
|
|
size_t len, unsigned long flags)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
struct scatterlist dst_sg;
|
|
struct scatterlist src_sg;
|
|
|
|
sg_init_table(&dst_sg, 1);
|
|
sg_init_table(&src_sg, 1);
|
|
|
|
sg_dma_address(&dst_sg) = dst;
|
|
sg_dma_address(&src_sg) = src;
|
|
|
|
sg_dma_len(&dst_sg) = len;
|
|
sg_dma_len(&src_sg) = len;
|
|
|
|
dev_dbg(dchan->device->dev, "%s(): %zu @ %pad -> %pad\n",
|
|
__func__, len, &src, &dst);
|
|
|
|
return nbpf_prep_sg(chan, &src_sg, &dst_sg, 1,
|
|
DMA_MEM_TO_MEM, flags);
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *nbpf_prep_slave_sg(
|
|
struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
|
|
enum dma_transfer_direction direction, unsigned long flags, void *context)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
struct scatterlist slave_sg;
|
|
|
|
dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
|
|
|
|
sg_init_table(&slave_sg, 1);
|
|
|
|
switch (direction) {
|
|
case DMA_MEM_TO_DEV:
|
|
sg_dma_address(&slave_sg) = chan->slave_dst_addr;
|
|
return nbpf_prep_sg(chan, sgl, &slave_sg, sg_len,
|
|
direction, flags);
|
|
|
|
case DMA_DEV_TO_MEM:
|
|
sg_dma_address(&slave_sg) = chan->slave_src_addr;
|
|
return nbpf_prep_sg(chan, &slave_sg, sgl, sg_len,
|
|
direction, flags);
|
|
|
|
default:
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
static int nbpf_alloc_chan_resources(struct dma_chan *dchan)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
int ret;
|
|
|
|
INIT_LIST_HEAD(&chan->free);
|
|
INIT_LIST_HEAD(&chan->free_links);
|
|
INIT_LIST_HEAD(&chan->queued);
|
|
INIT_LIST_HEAD(&chan->active);
|
|
INIT_LIST_HEAD(&chan->done);
|
|
|
|
ret = nbpf_desc_page_alloc(chan);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
dev_dbg(dchan->device->dev, "Entry %s(): terminal %u\n", __func__,
|
|
chan->terminal);
|
|
|
|
nbpf_chan_configure(chan);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void nbpf_free_chan_resources(struct dma_chan *dchan)
|
|
{
|
|
struct nbpf_channel *chan = nbpf_to_chan(dchan);
|
|
struct nbpf_desc_page *dpage, *tmp;
|
|
|
|
dev_dbg(dchan->device->dev, "Entry %s()\n", __func__);
|
|
|
|
nbpf_chan_halt(chan);
|
|
nbpf_chan_idle(chan);
|
|
/* Clean up for if a channel is re-used for MEMCPY after slave DMA */
|
|
nbpf_chan_prepare_default(chan);
|
|
|
|
list_for_each_entry_safe(dpage, tmp, &chan->desc_page, node) {
|
|
struct nbpf_link_desc *ldesc;
|
|
int i;
|
|
list_del(&dpage->node);
|
|
for (i = 0, ldesc = dpage->ldesc;
|
|
i < ARRAY_SIZE(dpage->ldesc);
|
|
i++, ldesc++)
|
|
dma_unmap_single(dchan->device->dev, ldesc->hwdesc_dma_addr,
|
|
sizeof(*ldesc->hwdesc), DMA_TO_DEVICE);
|
|
free_page((unsigned long)dpage);
|
|
}
|
|
}
|
|
|
|
static struct dma_chan *nbpf_of_xlate(struct of_phandle_args *dma_spec,
|
|
struct of_dma *ofdma)
|
|
{
|
|
struct nbpf_device *nbpf = ofdma->of_dma_data;
|
|
struct dma_chan *dchan;
|
|
struct nbpf_channel *chan;
|
|
|
|
if (dma_spec->args_count != 2)
|
|
return NULL;
|
|
|
|
dchan = dma_get_any_slave_channel(&nbpf->dma_dev);
|
|
if (!dchan)
|
|
return NULL;
|
|
|
|
dev_dbg(dchan->device->dev, "Entry %s(%pOFn)\n", __func__,
|
|
dma_spec->np);
|
|
|
|
chan = nbpf_to_chan(dchan);
|
|
|
|
chan->terminal = dma_spec->args[0];
|
|
chan->flags = dma_spec->args[1];
|
|
|
|
nbpf_chan_prepare(chan);
|
|
nbpf_chan_configure(chan);
|
|
|
|
return dchan;
|
|
}
|
|
|
|
static void nbpf_chan_tasklet(struct tasklet_struct *t)
|
|
{
|
|
struct nbpf_channel *chan = from_tasklet(chan, t, tasklet);
|
|
struct nbpf_desc *desc, *tmp;
|
|
struct dmaengine_desc_callback cb;
|
|
|
|
while (!list_empty(&chan->done)) {
|
|
bool found = false, must_put, recycling = false;
|
|
|
|
spin_lock_irq(&chan->lock);
|
|
|
|
list_for_each_entry_safe(desc, tmp, &chan->done, node) {
|
|
if (!desc->user_wait) {
|
|
/* Newly completed descriptor, have to process */
|
|
found = true;
|
|
break;
|
|
} else if (async_tx_test_ack(&desc->async_tx)) {
|
|
/*
|
|
* This descriptor was waiting for a user ACK,
|
|
* it can be recycled now.
|
|
*/
|
|
list_del(&desc->node);
|
|
spin_unlock_irq(&chan->lock);
|
|
nbpf_desc_put(desc);
|
|
recycling = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (recycling)
|
|
continue;
|
|
|
|
if (!found) {
|
|
/* This can happen if TERMINATE_ALL has been called */
|
|
spin_unlock_irq(&chan->lock);
|
|
break;
|
|
}
|
|
|
|
dma_cookie_complete(&desc->async_tx);
|
|
|
|
/*
|
|
* With released lock we cannot dereference desc, maybe it's
|
|
* still on the "done" list
|
|
*/
|
|
if (async_tx_test_ack(&desc->async_tx)) {
|
|
list_del(&desc->node);
|
|
must_put = true;
|
|
} else {
|
|
desc->user_wait = true;
|
|
must_put = false;
|
|
}
|
|
|
|
dmaengine_desc_get_callback(&desc->async_tx, &cb);
|
|
|
|
/* ack and callback completed descriptor */
|
|
spin_unlock_irq(&chan->lock);
|
|
|
|
dmaengine_desc_callback_invoke(&cb, NULL);
|
|
|
|
if (must_put)
|
|
nbpf_desc_put(desc);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t nbpf_chan_irq(int irq, void *dev)
|
|
{
|
|
struct nbpf_channel *chan = dev;
|
|
bool done = nbpf_status_get(chan);
|
|
struct nbpf_desc *desc;
|
|
irqreturn_t ret;
|
|
bool bh = false;
|
|
|
|
if (!done)
|
|
return IRQ_NONE;
|
|
|
|
nbpf_status_ack(chan);
|
|
|
|
dev_dbg(&chan->dma_chan.dev->device, "%s()\n", __func__);
|
|
|
|
spin_lock(&chan->lock);
|
|
desc = chan->running;
|
|
if (WARN_ON(!desc)) {
|
|
ret = IRQ_NONE;
|
|
goto unlock;
|
|
} else {
|
|
ret = IRQ_HANDLED;
|
|
bh = true;
|
|
}
|
|
|
|
list_move_tail(&desc->node, &chan->done);
|
|
chan->running = NULL;
|
|
|
|
if (!list_empty(&chan->active)) {
|
|
desc = list_first_entry(&chan->active,
|
|
struct nbpf_desc, node);
|
|
if (!nbpf_start(desc))
|
|
chan->running = desc;
|
|
}
|
|
|
|
unlock:
|
|
spin_unlock(&chan->lock);
|
|
|
|
if (bh)
|
|
tasklet_schedule(&chan->tasklet);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static irqreturn_t nbpf_err_irq(int irq, void *dev)
|
|
{
|
|
struct nbpf_device *nbpf = dev;
|
|
u32 error = nbpf_error_get(nbpf);
|
|
|
|
dev_warn(nbpf->dma_dev.dev, "DMA error IRQ %u\n", irq);
|
|
|
|
if (!error)
|
|
return IRQ_NONE;
|
|
|
|
do {
|
|
struct nbpf_channel *chan = nbpf_error_get_channel(nbpf, error);
|
|
/* On error: abort all queued transfers, no callback */
|
|
nbpf_error_clear(chan);
|
|
nbpf_chan_idle(chan);
|
|
error = nbpf_error_get(nbpf);
|
|
} while (error);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int nbpf_chan_probe(struct nbpf_device *nbpf, int n)
|
|
{
|
|
struct dma_device *dma_dev = &nbpf->dma_dev;
|
|
struct nbpf_channel *chan = nbpf->chan + n;
|
|
int ret;
|
|
|
|
chan->nbpf = nbpf;
|
|
chan->base = nbpf->base + NBPF_REG_CHAN_OFFSET + NBPF_REG_CHAN_SIZE * n;
|
|
INIT_LIST_HEAD(&chan->desc_page);
|
|
spin_lock_init(&chan->lock);
|
|
chan->dma_chan.device = dma_dev;
|
|
dma_cookie_init(&chan->dma_chan);
|
|
nbpf_chan_prepare_default(chan);
|
|
|
|
dev_dbg(dma_dev->dev, "%s(): channel %d: -> %p\n", __func__, n, chan->base);
|
|
|
|
snprintf(chan->name, sizeof(chan->name), "nbpf %d", n);
|
|
|
|
tasklet_setup(&chan->tasklet, nbpf_chan_tasklet);
|
|
ret = devm_request_irq(dma_dev->dev, chan->irq,
|
|
nbpf_chan_irq, IRQF_SHARED,
|
|
chan->name, chan);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Add the channel to DMA device channel list */
|
|
list_add_tail(&chan->dma_chan.device_node,
|
|
&dma_dev->channels);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id nbpf_match[] = {
|
|
{.compatible = "renesas,nbpfaxi64dmac1b4", .data = &nbpf_cfg[NBPF1B4]},
|
|
{.compatible = "renesas,nbpfaxi64dmac1b8", .data = &nbpf_cfg[NBPF1B8]},
|
|
{.compatible = "renesas,nbpfaxi64dmac1b16", .data = &nbpf_cfg[NBPF1B16]},
|
|
{.compatible = "renesas,nbpfaxi64dmac4b4", .data = &nbpf_cfg[NBPF4B4]},
|
|
{.compatible = "renesas,nbpfaxi64dmac4b8", .data = &nbpf_cfg[NBPF4B8]},
|
|
{.compatible = "renesas,nbpfaxi64dmac4b16", .data = &nbpf_cfg[NBPF4B16]},
|
|
{.compatible = "renesas,nbpfaxi64dmac8b4", .data = &nbpf_cfg[NBPF8B4]},
|
|
{.compatible = "renesas,nbpfaxi64dmac8b8", .data = &nbpf_cfg[NBPF8B8]},
|
|
{.compatible = "renesas,nbpfaxi64dmac8b16", .data = &nbpf_cfg[NBPF8B16]},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, nbpf_match);
|
|
|
|
static int nbpf_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct nbpf_device *nbpf;
|
|
struct dma_device *dma_dev;
|
|
struct resource *iomem;
|
|
const struct nbpf_config *cfg;
|
|
int num_channels;
|
|
int ret, irq, eirq, i;
|
|
int irqbuf[9] /* maximum 8 channels + error IRQ */;
|
|
unsigned int irqs = 0;
|
|
|
|
BUILD_BUG_ON(sizeof(struct nbpf_desc_page) > PAGE_SIZE);
|
|
|
|
/* DT only */
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
cfg = of_device_get_match_data(dev);
|
|
num_channels = cfg->num_channels;
|
|
|
|
nbpf = devm_kzalloc(dev, struct_size(nbpf, chan, num_channels),
|
|
GFP_KERNEL);
|
|
if (!nbpf)
|
|
return -ENOMEM;
|
|
|
|
dma_dev = &nbpf->dma_dev;
|
|
dma_dev->dev = dev;
|
|
|
|
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
nbpf->base = devm_ioremap_resource(dev, iomem);
|
|
if (IS_ERR(nbpf->base))
|
|
return PTR_ERR(nbpf->base);
|
|
|
|
nbpf->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(nbpf->clk))
|
|
return PTR_ERR(nbpf->clk);
|
|
|
|
of_property_read_u32(np, "max-burst-mem-read",
|
|
&nbpf->max_burst_mem_read);
|
|
of_property_read_u32(np, "max-burst-mem-write",
|
|
&nbpf->max_burst_mem_write);
|
|
|
|
nbpf->config = cfg;
|
|
|
|
for (i = 0; irqs < ARRAY_SIZE(irqbuf); i++) {
|
|
irq = platform_get_irq_optional(pdev, i);
|
|
if (irq < 0 && irq != -ENXIO)
|
|
return irq;
|
|
if (irq > 0)
|
|
irqbuf[irqs++] = irq;
|
|
}
|
|
|
|
/*
|
|
* 3 IRQ resource schemes are supported:
|
|
* 1. 1 shared IRQ for error and all channels
|
|
* 2. 2 IRQs: one for error and one shared for all channels
|
|
* 3. 1 IRQ for error and an own IRQ for each channel
|
|
*/
|
|
if (irqs != 1 && irqs != 2 && irqs != num_channels + 1)
|
|
return -ENXIO;
|
|
|
|
if (irqs == 1) {
|
|
eirq = irqbuf[0];
|
|
|
|
for (i = 0; i <= num_channels; i++)
|
|
nbpf->chan[i].irq = irqbuf[0];
|
|
} else {
|
|
eirq = platform_get_irq_byname(pdev, "error");
|
|
if (eirq < 0)
|
|
return eirq;
|
|
|
|
if (irqs == num_channels + 1) {
|
|
struct nbpf_channel *chan;
|
|
|
|
for (i = 0, chan = nbpf->chan; i <= num_channels;
|
|
i++, chan++) {
|
|
/* Skip the error IRQ */
|
|
if (irqbuf[i] == eirq)
|
|
i++;
|
|
chan->irq = irqbuf[i];
|
|
}
|
|
|
|
if (chan != nbpf->chan + num_channels)
|
|
return -EINVAL;
|
|
} else {
|
|
/* 2 IRQs and more than one channel */
|
|
if (irqbuf[0] == eirq)
|
|
irq = irqbuf[1];
|
|
else
|
|
irq = irqbuf[0];
|
|
|
|
for (i = 0; i <= num_channels; i++)
|
|
nbpf->chan[i].irq = irq;
|
|
}
|
|
}
|
|
|
|
ret = devm_request_irq(dev, eirq, nbpf_err_irq,
|
|
IRQF_SHARED, "dma error", nbpf);
|
|
if (ret < 0)
|
|
return ret;
|
|
nbpf->eirq = eirq;
|
|
|
|
INIT_LIST_HEAD(&dma_dev->channels);
|
|
|
|
/* Create DMA Channel */
|
|
for (i = 0; i < num_channels; i++) {
|
|
ret = nbpf_chan_probe(nbpf, i);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
|
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
|
|
dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
|
|
|
|
/* Common and MEMCPY operations */
|
|
dma_dev->device_alloc_chan_resources
|
|
= nbpf_alloc_chan_resources;
|
|
dma_dev->device_free_chan_resources = nbpf_free_chan_resources;
|
|
dma_dev->device_prep_dma_memcpy = nbpf_prep_memcpy;
|
|
dma_dev->device_tx_status = nbpf_tx_status;
|
|
dma_dev->device_issue_pending = nbpf_issue_pending;
|
|
|
|
/*
|
|
* If we drop support for unaligned MEMCPY buffer addresses and / or
|
|
* lengths by setting
|
|
* dma_dev->copy_align = 4;
|
|
* then we can set transfer length to 4 bytes in nbpf_prep_one() for
|
|
* DMA_MEM_TO_MEM
|
|
*/
|
|
|
|
/* Compulsory for DMA_SLAVE fields */
|
|
dma_dev->device_prep_slave_sg = nbpf_prep_slave_sg;
|
|
dma_dev->device_config = nbpf_config;
|
|
dma_dev->device_pause = nbpf_pause;
|
|
dma_dev->device_terminate_all = nbpf_terminate_all;
|
|
|
|
dma_dev->src_addr_widths = NBPF_DMA_BUSWIDTHS;
|
|
dma_dev->dst_addr_widths = NBPF_DMA_BUSWIDTHS;
|
|
dma_dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
|
|
|
platform_set_drvdata(pdev, nbpf);
|
|
|
|
ret = clk_prepare_enable(nbpf->clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
nbpf_configure(nbpf);
|
|
|
|
ret = dma_async_device_register(dma_dev);
|
|
if (ret < 0)
|
|
goto e_clk_off;
|
|
|
|
ret = of_dma_controller_register(np, nbpf_of_xlate, nbpf);
|
|
if (ret < 0)
|
|
goto e_dma_dev_unreg;
|
|
|
|
return 0;
|
|
|
|
e_dma_dev_unreg:
|
|
dma_async_device_unregister(dma_dev);
|
|
e_clk_off:
|
|
clk_disable_unprepare(nbpf->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int nbpf_remove(struct platform_device *pdev)
|
|
{
|
|
struct nbpf_device *nbpf = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
devm_free_irq(&pdev->dev, nbpf->eirq, nbpf);
|
|
|
|
for (i = 0; i < nbpf->config->num_channels; i++) {
|
|
struct nbpf_channel *chan = nbpf->chan + i;
|
|
|
|
devm_free_irq(&pdev->dev, chan->irq, chan);
|
|
|
|
tasklet_kill(&chan->tasklet);
|
|
}
|
|
|
|
of_dma_controller_free(pdev->dev.of_node);
|
|
dma_async_device_unregister(&nbpf->dma_dev);
|
|
clk_disable_unprepare(nbpf->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id nbpf_ids[] = {
|
|
{"nbpfaxi64dmac1b4", (kernel_ulong_t)&nbpf_cfg[NBPF1B4]},
|
|
{"nbpfaxi64dmac1b8", (kernel_ulong_t)&nbpf_cfg[NBPF1B8]},
|
|
{"nbpfaxi64dmac1b16", (kernel_ulong_t)&nbpf_cfg[NBPF1B16]},
|
|
{"nbpfaxi64dmac4b4", (kernel_ulong_t)&nbpf_cfg[NBPF4B4]},
|
|
{"nbpfaxi64dmac4b8", (kernel_ulong_t)&nbpf_cfg[NBPF4B8]},
|
|
{"nbpfaxi64dmac4b16", (kernel_ulong_t)&nbpf_cfg[NBPF4B16]},
|
|
{"nbpfaxi64dmac8b4", (kernel_ulong_t)&nbpf_cfg[NBPF8B4]},
|
|
{"nbpfaxi64dmac8b8", (kernel_ulong_t)&nbpf_cfg[NBPF8B8]},
|
|
{"nbpfaxi64dmac8b16", (kernel_ulong_t)&nbpf_cfg[NBPF8B16]},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, nbpf_ids);
|
|
|
|
#ifdef CONFIG_PM
|
|
static int nbpf_runtime_suspend(struct device *dev)
|
|
{
|
|
struct nbpf_device *nbpf = dev_get_drvdata(dev);
|
|
clk_disable_unprepare(nbpf->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int nbpf_runtime_resume(struct device *dev)
|
|
{
|
|
struct nbpf_device *nbpf = dev_get_drvdata(dev);
|
|
return clk_prepare_enable(nbpf->clk);
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops nbpf_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(nbpf_runtime_suspend, nbpf_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver nbpf_driver = {
|
|
.driver = {
|
|
.name = "dma-nbpf",
|
|
.of_match_table = nbpf_match,
|
|
.pm = &nbpf_pm_ops,
|
|
},
|
|
.id_table = nbpf_ids,
|
|
.probe = nbpf_probe,
|
|
.remove = nbpf_remove,
|
|
};
|
|
|
|
module_platform_driver(nbpf_driver);
|
|
|
|
MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
|
|
MODULE_DESCRIPTION("dmaengine driver for NBPFAXI64* DMACs");
|
|
MODULE_LICENSE("GPL v2");
|