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![Tom Rix](/assets/img/avatar_default.png)
Run the fpga subsystem through aspell. Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Fernando Pacheco <fpacheco@redhat.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>
478 lines
11 KiB
C
478 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for FPGA Management Engine (FME) Partial Reconfiguration
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*
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* Copyright (C) 2017-2018 Intel Corporation, Inc.
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*
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* Authors:
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* Kang Luwei <luwei.kang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Wu Hao <hao.wu@intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Christopher Rauer <christopher.rauer@intel.com>
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* Henry Mitchel <henry.mitchel@intel.com>
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*/
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/vmalloc.h>
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#include <linux/uaccess.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/fpga/fpga-bridge.h>
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#include <linux/fpga/fpga-region.h>
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#include <linux/fpga-dfl.h>
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#include "dfl.h"
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#include "dfl-fme.h"
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#include "dfl-fme-pr.h"
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static struct dfl_fme_region *
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dfl_fme_region_find_by_port_id(struct dfl_fme *fme, int port_id)
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{
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struct dfl_fme_region *fme_region;
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list_for_each_entry(fme_region, &fme->region_list, node)
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if (fme_region->port_id == port_id)
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return fme_region;
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return NULL;
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}
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static int dfl_fme_region_match(struct device *dev, const void *data)
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{
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return dev->parent == data;
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}
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static struct fpga_region *dfl_fme_region_find(struct dfl_fme *fme, int port_id)
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{
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struct dfl_fme_region *fme_region;
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struct fpga_region *region;
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fme_region = dfl_fme_region_find_by_port_id(fme, port_id);
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if (!fme_region)
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return NULL;
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region = fpga_region_class_find(NULL, &fme_region->region->dev,
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dfl_fme_region_match);
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if (!region)
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return NULL;
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return region;
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}
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static int fme_pr(struct platform_device *pdev, unsigned long arg)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
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void __user *argp = (void __user *)arg;
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struct dfl_fpga_fme_port_pr port_pr;
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struct fpga_image_info *info;
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struct fpga_region *region;
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void __iomem *fme_hdr;
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struct dfl_fme *fme;
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unsigned long minsz;
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void *buf = NULL;
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size_t length;
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int ret = 0;
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u64 v;
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minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);
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if (copy_from_user(&port_pr, argp, minsz))
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return -EFAULT;
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if (port_pr.argsz < minsz || port_pr.flags)
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return -EINVAL;
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/* get fme header region */
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fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
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FME_FEATURE_ID_HEADER);
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/* check port id */
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v = readq(fme_hdr + FME_HDR_CAP);
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if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
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dev_dbg(&pdev->dev, "port number more than maximum\n");
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return -EINVAL;
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}
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/*
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* align PR buffer per PR bandwidth, as HW ignores the extra padding
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* data automatically.
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*/
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length = ALIGN(port_pr.buffer_size, 4);
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buf = vmalloc(length);
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if (!buf)
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return -ENOMEM;
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if (copy_from_user(buf,
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(void __user *)(unsigned long)port_pr.buffer_address,
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port_pr.buffer_size)) {
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ret = -EFAULT;
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goto free_exit;
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}
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/* prepare fpga_image_info for PR */
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info = fpga_image_info_alloc(&pdev->dev);
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if (!info) {
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ret = -ENOMEM;
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goto free_exit;
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}
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info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
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mutex_lock(&pdata->lock);
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fme = dfl_fpga_pdata_get_private(pdata);
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/* fme device has been unregistered. */
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if (!fme) {
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ret = -EINVAL;
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goto unlock_exit;
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}
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region = dfl_fme_region_find(fme, port_pr.port_id);
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if (!region) {
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ret = -EINVAL;
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goto unlock_exit;
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}
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fpga_image_info_free(region->info);
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info->buf = buf;
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info->count = length;
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info->region_id = port_pr.port_id;
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region->info = info;
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ret = fpga_region_program_fpga(region);
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/*
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* it allows userspace to reset the PR region's logic by disabling and
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* reenabling the bridge to clear things out between acceleration runs.
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* so no need to hold the bridges after partial reconfiguration.
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*/
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if (region->get_bridges)
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fpga_bridges_put(®ion->bridge_list);
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put_device(®ion->dev);
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unlock_exit:
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mutex_unlock(&pdata->lock);
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free_exit:
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vfree(buf);
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return ret;
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}
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/**
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* dfl_fme_create_mgr - create fpga mgr platform device as child device
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*
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* @pdata: fme platform_device's pdata
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*
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* Return: mgr platform device if successful, and error code otherwise.
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*/
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static struct platform_device *
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dfl_fme_create_mgr(struct dfl_feature_platform_data *pdata,
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struct dfl_feature *feature)
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{
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struct platform_device *mgr, *fme = pdata->dev;
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struct dfl_fme_mgr_pdata mgr_pdata;
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int ret = -ENOMEM;
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if (!feature->ioaddr)
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return ERR_PTR(-ENODEV);
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mgr_pdata.ioaddr = feature->ioaddr;
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/*
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* Each FME has only one fpga-mgr, so allocate platform device using
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* the same FME platform device id.
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*/
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mgr = platform_device_alloc(DFL_FPGA_FME_MGR, fme->id);
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if (!mgr)
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return ERR_PTR(ret);
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mgr->dev.parent = &fme->dev;
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ret = platform_device_add_data(mgr, &mgr_pdata, sizeof(mgr_pdata));
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if (ret)
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goto create_mgr_err;
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ret = platform_device_add(mgr);
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if (ret)
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goto create_mgr_err;
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return mgr;
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create_mgr_err:
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platform_device_put(mgr);
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return ERR_PTR(ret);
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}
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/**
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* dfl_fme_destroy_mgr - destroy fpga mgr platform device
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* @pdata: fme platform device's pdata
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*/
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static void dfl_fme_destroy_mgr(struct dfl_feature_platform_data *pdata)
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{
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struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
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platform_device_unregister(priv->mgr);
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}
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/**
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* dfl_fme_create_bridge - create fme fpga bridge platform device as child
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*
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* @pdata: fme platform device's pdata
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* @port_id: port id for the bridge to be created.
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*
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* Return: bridge platform device if successful, and error code otherwise.
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*/
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static struct dfl_fme_bridge *
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dfl_fme_create_bridge(struct dfl_feature_platform_data *pdata, int port_id)
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{
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struct device *dev = &pdata->dev->dev;
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struct dfl_fme_br_pdata br_pdata;
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struct dfl_fme_bridge *fme_br;
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int ret = -ENOMEM;
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fme_br = devm_kzalloc(dev, sizeof(*fme_br), GFP_KERNEL);
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if (!fme_br)
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return ERR_PTR(ret);
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br_pdata.cdev = pdata->dfl_cdev;
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br_pdata.port_id = port_id;
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fme_br->br = platform_device_alloc(DFL_FPGA_FME_BRIDGE,
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PLATFORM_DEVID_AUTO);
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if (!fme_br->br)
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return ERR_PTR(ret);
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fme_br->br->dev.parent = dev;
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ret = platform_device_add_data(fme_br->br, &br_pdata, sizeof(br_pdata));
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if (ret)
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goto create_br_err;
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ret = platform_device_add(fme_br->br);
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if (ret)
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goto create_br_err;
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return fme_br;
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create_br_err:
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platform_device_put(fme_br->br);
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return ERR_PTR(ret);
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}
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/**
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* dfl_fme_destroy_bridge - destroy fpga bridge platform device
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* @fme_br: fme bridge to destroy
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*/
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static void dfl_fme_destroy_bridge(struct dfl_fme_bridge *fme_br)
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{
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platform_device_unregister(fme_br->br);
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}
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/**
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* dfl_fme_destroy_bridge - destroy all fpga bridge platform device
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* @pdata: fme platform device's pdata
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*/
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static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata)
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{
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struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
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struct dfl_fme_bridge *fbridge, *tmp;
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list_for_each_entry_safe(fbridge, tmp, &priv->bridge_list, node) {
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list_del(&fbridge->node);
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dfl_fme_destroy_bridge(fbridge);
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}
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}
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/**
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* dfl_fme_create_region - create fpga region platform device as child
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*
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* @pdata: fme platform device's pdata
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* @mgr: mgr platform device needed for region
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* @br: br platform device needed for region
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* @port_id: port id
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*
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* Return: fme region if successful, and error code otherwise.
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*/
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static struct dfl_fme_region *
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dfl_fme_create_region(struct dfl_feature_platform_data *pdata,
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struct platform_device *mgr,
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struct platform_device *br, int port_id)
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{
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struct dfl_fme_region_pdata region_pdata;
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struct device *dev = &pdata->dev->dev;
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struct dfl_fme_region *fme_region;
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int ret = -ENOMEM;
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fme_region = devm_kzalloc(dev, sizeof(*fme_region), GFP_KERNEL);
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if (!fme_region)
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return ERR_PTR(ret);
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region_pdata.mgr = mgr;
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region_pdata.br = br;
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/*
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* Each FPGA device may have more than one port, so allocate platform
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* device using the same port platform device id.
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*/
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fme_region->region = platform_device_alloc(DFL_FPGA_FME_REGION, br->id);
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if (!fme_region->region)
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return ERR_PTR(ret);
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fme_region->region->dev.parent = dev;
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ret = platform_device_add_data(fme_region->region, ®ion_pdata,
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sizeof(region_pdata));
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if (ret)
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goto create_region_err;
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ret = platform_device_add(fme_region->region);
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if (ret)
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goto create_region_err;
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fme_region->port_id = port_id;
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return fme_region;
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create_region_err:
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platform_device_put(fme_region->region);
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return ERR_PTR(ret);
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}
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/**
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* dfl_fme_destroy_region - destroy fme region
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* @fme_region: fme region to destroy
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*/
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static void dfl_fme_destroy_region(struct dfl_fme_region *fme_region)
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{
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platform_device_unregister(fme_region->region);
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}
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/**
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* dfl_fme_destroy_regions - destroy all fme regions
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* @pdata: fme platform device's pdata
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*/
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static void dfl_fme_destroy_regions(struct dfl_feature_platform_data *pdata)
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{
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struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
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struct dfl_fme_region *fme_region, *tmp;
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list_for_each_entry_safe(fme_region, tmp, &priv->region_list, node) {
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list_del(&fme_region->node);
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dfl_fme_destroy_region(fme_region);
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}
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}
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static int pr_mgmt_init(struct platform_device *pdev,
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struct dfl_feature *feature)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct dfl_fme_region *fme_region;
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struct dfl_fme_bridge *fme_br;
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struct platform_device *mgr;
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struct dfl_fme *priv;
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void __iomem *fme_hdr;
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int ret = -ENODEV, i = 0;
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u64 fme_cap, port_offset;
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fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
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FME_FEATURE_ID_HEADER);
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mutex_lock(&pdata->lock);
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priv = dfl_fpga_pdata_get_private(pdata);
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/* Initialize the region and bridge sub device list */
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INIT_LIST_HEAD(&priv->region_list);
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INIT_LIST_HEAD(&priv->bridge_list);
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/* Create fpga mgr platform device */
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mgr = dfl_fme_create_mgr(pdata, feature);
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if (IS_ERR(mgr)) {
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dev_err(&pdev->dev, "fail to create fpga mgr pdev\n");
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goto unlock;
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}
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priv->mgr = mgr;
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/* Read capability register to check number of regions and bridges */
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fme_cap = readq(fme_hdr + FME_HDR_CAP);
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for (; i < FIELD_GET(FME_CAP_NUM_PORTS, fme_cap); i++) {
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port_offset = readq(fme_hdr + FME_HDR_PORT_OFST(i));
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if (!(port_offset & FME_PORT_OFST_IMP))
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continue;
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/* Create bridge for each port */
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fme_br = dfl_fme_create_bridge(pdata, i);
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if (IS_ERR(fme_br)) {
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ret = PTR_ERR(fme_br);
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goto destroy_region;
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}
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list_add(&fme_br->node, &priv->bridge_list);
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/* Create region for each port */
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fme_region = dfl_fme_create_region(pdata, mgr,
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fme_br->br, i);
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if (IS_ERR(fme_region)) {
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ret = PTR_ERR(fme_region);
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goto destroy_region;
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}
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list_add(&fme_region->node, &priv->region_list);
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}
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mutex_unlock(&pdata->lock);
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return 0;
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destroy_region:
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dfl_fme_destroy_regions(pdata);
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dfl_fme_destroy_bridges(pdata);
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dfl_fme_destroy_mgr(pdata);
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unlock:
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mutex_unlock(&pdata->lock);
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return ret;
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}
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static void pr_mgmt_uinit(struct platform_device *pdev,
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struct dfl_feature *feature)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
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mutex_lock(&pdata->lock);
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dfl_fme_destroy_regions(pdata);
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dfl_fme_destroy_bridges(pdata);
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dfl_fme_destroy_mgr(pdata);
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mutex_unlock(&pdata->lock);
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}
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static long fme_pr_ioctl(struct platform_device *pdev,
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struct dfl_feature *feature,
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unsigned int cmd, unsigned long arg)
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{
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long ret;
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switch (cmd) {
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case DFL_FPGA_FME_PORT_PR:
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ret = fme_pr(pdev, arg);
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break;
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default:
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ret = -ENODEV;
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}
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return ret;
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}
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const struct dfl_feature_id fme_pr_mgmt_id_table[] = {
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{.id = FME_FEATURE_ID_PR_MGMT,},
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{0}
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};
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const struct dfl_feature_ops fme_pr_mgmt_ops = {
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.init = pr_mgmt_init,
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.uinit = pr_mgmt_uinit,
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.ioctl = fme_pr_ioctl,
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};
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