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![Lu Baolu](/assets/img/avatar_default.png)
Move the domain specific operations out of struct iommu_ops into a new structure that only has domain specific operations. This solves the problem of needing to know if the method vector for a given operation needs to be retrieved from the device or the domain. Logically the domain ops are the ones that make sense for external subsystems and endpoint drivers to use, while device ops, with the sole exception of domain_alloc, are IOMMU API internals. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Link: https://lore.kernel.org/r/20220216025249.3459465-10-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
376 lines
9 KiB
C
376 lines
9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* IOMMU API for Graphics Address Relocation Table on Tegra20
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*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Hiroshi DOYU <hdoyu@nvidia.com>
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*/
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#define dev_fmt(fmt) "gart: " fmt
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/vmalloc.h>
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#include <soc/tegra/mc.h>
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#define GART_REG_BASE 0x24
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#define GART_CONFIG (0x24 - GART_REG_BASE)
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#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
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#define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
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#define GART_ENTRY_PHYS_ADDR_VALID BIT(31)
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#define GART_PAGE_SHIFT 12
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#define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT)
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#define GART_PAGE_MASK GENMASK(30, GART_PAGE_SHIFT)
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/* bitmap of the page sizes currently supported */
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#define GART_IOMMU_PGSIZES (GART_PAGE_SIZE)
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struct gart_device {
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void __iomem *regs;
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u32 *savedata;
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unsigned long iovmm_base; /* offset to vmm_area start */
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unsigned long iovmm_end; /* offset to vmm_area end */
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spinlock_t pte_lock; /* for pagetable */
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spinlock_t dom_lock; /* for active domain */
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unsigned int active_devices; /* number of active devices */
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struct iommu_domain *active_domain; /* current active domain */
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struct iommu_device iommu; /* IOMMU Core handle */
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struct device *dev;
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};
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static struct gart_device *gart_handle; /* unique for a system */
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static bool gart_debug;
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/*
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* Any interaction between any block on PPSB and a block on APB or AHB
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* must have these read-back to ensure the APB/AHB bus transaction is
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* complete before initiating activity on the PPSB block.
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*/
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#define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG)
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#define for_each_gart_pte(gart, iova) \
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for (iova = gart->iovmm_base; \
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iova < gart->iovmm_end; \
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iova += GART_PAGE_SIZE)
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static inline void gart_set_pte(struct gart_device *gart,
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unsigned long iova, unsigned long pte)
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{
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writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR);
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writel_relaxed(pte, gart->regs + GART_ENTRY_DATA);
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}
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static inline unsigned long gart_read_pte(struct gart_device *gart,
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unsigned long iova)
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{
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unsigned long pte;
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writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR);
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pte = readl_relaxed(gart->regs + GART_ENTRY_DATA);
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return pte;
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}
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static void do_gart_setup(struct gart_device *gart, const u32 *data)
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{
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unsigned long iova;
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for_each_gart_pte(gart, iova)
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gart_set_pte(gart, iova, data ? *(data++) : 0);
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writel_relaxed(1, gart->regs + GART_CONFIG);
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FLUSH_GART_REGS(gart);
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}
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static inline bool gart_iova_range_invalid(struct gart_device *gart,
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unsigned long iova, size_t bytes)
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{
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return unlikely(iova < gart->iovmm_base || bytes != GART_PAGE_SIZE ||
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iova + bytes > gart->iovmm_end);
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}
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static inline bool gart_pte_valid(struct gart_device *gart, unsigned long iova)
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{
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return !!(gart_read_pte(gart, iova) & GART_ENTRY_PHYS_ADDR_VALID);
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}
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static int gart_iommu_attach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct gart_device *gart = gart_handle;
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int ret = 0;
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spin_lock(&gart->dom_lock);
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if (gart->active_domain && gart->active_domain != domain) {
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ret = -EBUSY;
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} else if (dev_iommu_priv_get(dev) != domain) {
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dev_iommu_priv_set(dev, domain);
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gart->active_domain = domain;
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gart->active_devices++;
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}
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spin_unlock(&gart->dom_lock);
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return ret;
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}
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static void gart_iommu_detach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct gart_device *gart = gart_handle;
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spin_lock(&gart->dom_lock);
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if (dev_iommu_priv_get(dev) == domain) {
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dev_iommu_priv_set(dev, NULL);
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if (--gart->active_devices == 0)
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gart->active_domain = NULL;
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}
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spin_unlock(&gart->dom_lock);
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}
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static struct iommu_domain *gart_iommu_domain_alloc(unsigned type)
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{
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struct iommu_domain *domain;
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if (type != IOMMU_DOMAIN_UNMANAGED)
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return NULL;
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domain = kzalloc(sizeof(*domain), GFP_KERNEL);
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if (domain) {
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domain->geometry.aperture_start = gart_handle->iovmm_base;
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domain->geometry.aperture_end = gart_handle->iovmm_end - 1;
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domain->geometry.force_aperture = true;
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}
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return domain;
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}
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static void gart_iommu_domain_free(struct iommu_domain *domain)
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{
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WARN_ON(gart_handle->active_domain == domain);
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kfree(domain);
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}
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static inline int __gart_iommu_map(struct gart_device *gart, unsigned long iova,
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unsigned long pa)
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{
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if (unlikely(gart_debug && gart_pte_valid(gart, iova))) {
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dev_err(gart->dev, "Page entry is in-use\n");
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return -EINVAL;
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}
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gart_set_pte(gart, iova, GART_ENTRY_PHYS_ADDR_VALID | pa);
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return 0;
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}
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static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t pa, size_t bytes, int prot, gfp_t gfp)
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{
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struct gart_device *gart = gart_handle;
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int ret;
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if (gart_iova_range_invalid(gart, iova, bytes))
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return -EINVAL;
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spin_lock(&gart->pte_lock);
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ret = __gart_iommu_map(gart, iova, (unsigned long)pa);
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spin_unlock(&gart->pte_lock);
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return ret;
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}
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static inline int __gart_iommu_unmap(struct gart_device *gart,
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unsigned long iova)
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{
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if (unlikely(gart_debug && !gart_pte_valid(gart, iova))) {
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dev_err(gart->dev, "Page entry is invalid\n");
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return -EINVAL;
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}
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gart_set_pte(gart, iova, 0);
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return 0;
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}
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static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
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size_t bytes, struct iommu_iotlb_gather *gather)
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{
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struct gart_device *gart = gart_handle;
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int err;
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if (gart_iova_range_invalid(gart, iova, bytes))
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return 0;
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spin_lock(&gart->pte_lock);
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err = __gart_iommu_unmap(gart, iova);
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spin_unlock(&gart->pte_lock);
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return err ? 0 : bytes;
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}
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static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
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dma_addr_t iova)
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{
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struct gart_device *gart = gart_handle;
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unsigned long pte;
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if (gart_iova_range_invalid(gart, iova, GART_PAGE_SIZE))
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return -EINVAL;
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spin_lock(&gart->pte_lock);
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pte = gart_read_pte(gart, iova);
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spin_unlock(&gart->pte_lock);
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return pte & GART_PAGE_MASK;
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}
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static struct iommu_device *gart_iommu_probe_device(struct device *dev)
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{
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if (!dev_iommu_fwspec_get(dev))
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return ERR_PTR(-ENODEV);
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return &gart_handle->iommu;
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}
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static void gart_iommu_release_device(struct device *dev)
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{
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}
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static int gart_iommu_of_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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return 0;
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}
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static void gart_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
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size_t size)
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{
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FLUSH_GART_REGS(gart_handle);
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}
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static void gart_iommu_sync(struct iommu_domain *domain,
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struct iommu_iotlb_gather *gather)
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{
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size_t length = gather->end - gather->start + 1;
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gart_iommu_sync_map(domain, gather->start, length);
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}
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static const struct iommu_ops gart_iommu_ops = {
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.domain_alloc = gart_iommu_domain_alloc,
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.probe_device = gart_iommu_probe_device,
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.release_device = gart_iommu_release_device,
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.device_group = generic_device_group,
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.pgsize_bitmap = GART_IOMMU_PGSIZES,
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.of_xlate = gart_iommu_of_xlate,
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.default_domain_ops = &(const struct iommu_domain_ops) {
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.attach_dev = gart_iommu_attach_dev,
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.detach_dev = gart_iommu_detach_dev,
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.map = gart_iommu_map,
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.unmap = gart_iommu_unmap,
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.iova_to_phys = gart_iommu_iova_to_phys,
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.iotlb_sync_map = gart_iommu_sync_map,
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.iotlb_sync = gart_iommu_sync,
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.free = gart_iommu_domain_free,
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}
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};
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int tegra_gart_suspend(struct gart_device *gart)
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{
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u32 *data = gart->savedata;
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unsigned long iova;
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/*
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* All GART users shall be suspended at this point. Disable
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* address translation to trap all GART accesses as invalid
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* memory accesses.
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*/
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writel_relaxed(0, gart->regs + GART_CONFIG);
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FLUSH_GART_REGS(gart);
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for_each_gart_pte(gart, iova)
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*(data++) = gart_read_pte(gart, iova);
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return 0;
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}
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int tegra_gart_resume(struct gart_device *gart)
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{
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do_gart_setup(gart, gart->savedata);
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return 0;
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}
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struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
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{
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struct gart_device *gart;
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struct resource *res;
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int err;
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BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
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/* the GART memory aperture is required */
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res = platform_get_resource(to_platform_device(dev), IORESOURCE_MEM, 1);
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if (!res) {
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dev_err(dev, "Memory aperture resource unavailable\n");
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return ERR_PTR(-ENXIO);
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}
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gart = kzalloc(sizeof(*gart), GFP_KERNEL);
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if (!gart)
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return ERR_PTR(-ENOMEM);
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gart_handle = gart;
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gart->dev = dev;
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gart->regs = mc->regs + GART_REG_BASE;
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gart->iovmm_base = res->start;
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gart->iovmm_end = res->end + 1;
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spin_lock_init(&gart->pte_lock);
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spin_lock_init(&gart->dom_lock);
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do_gart_setup(gart, NULL);
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err = iommu_device_sysfs_add(&gart->iommu, dev, NULL, "gart");
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if (err)
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goto free_gart;
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err = iommu_device_register(&gart->iommu, &gart_iommu_ops, dev);
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if (err)
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goto remove_sysfs;
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gart->savedata = vmalloc(resource_size(res) / GART_PAGE_SIZE *
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sizeof(u32));
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if (!gart->savedata) {
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err = -ENOMEM;
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goto unregister_iommu;
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}
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return gart;
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unregister_iommu:
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iommu_device_unregister(&gart->iommu);
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remove_sysfs:
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iommu_device_sysfs_remove(&gart->iommu);
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free_gart:
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kfree(gart);
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return ERR_PTR(err);
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}
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module_param(gart_debug, bool, 0644);
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MODULE_PARM_DESC(gart_debug, "Enable GART debugging");
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