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![Linus Torvalds](/assets/img/avatar_default.png)
Updates for IRQ stacks and virtually mapped stack support for ARM from the following pull requests, etc: 1) ARM: support for IRQ and vmap'ed stacks This PR covers all the work related to implementing IRQ stacks and vmap'ed stacks for all 32-bit ARM systems that are currently supported by the Linux kernel, including RiscPC and Footbridge. It has been submitted for review in three different waves: - IRQ stacks support for v7 SMP systems [0], - vmap'ed stacks support for v7 SMP systems[1], - extending support for both IRQ stacks and vmap'ed stacks for all remaining configurations, including v6/v7 SMP multiplatform kernels and uniprocessor configurations including v7-M [2] [0] https://lore.kernel.org/linux-arm-kernel/20211115084732.3704393-1-ardb@kernel.org/ [1] https://lore.kernel.org/linux-arm-kernel/20211122092816.2865873-1-ardb@kernel.org/ [2] https://lore.kernel.org/linux-arm-kernel/20211206164659.1495084-1-ardb@kernel.org/ 2) ARM: support for IRQ and vmap'ed stacks [v6] This tag covers the changes between the version of vmap'ed + IRQ stacks support pulled into rmk/devel-stable [0] (which was dropped from v5.17 due to issues discovered too late in the cycle), and my v5 proposed for the v5.18 cycle [1]. [0] git://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git arm-irq-and-vmap-stacks-for-rmk [1] https://lore.kernel.org/linux-arm-kernel/20220124174744.1054712-1-ardb@kernel.org/ 3) ARM: ftrace fixes and cleanups Make all flavors of ftrace available on all builds, regardless of ISA choice, unwinder choice or compiler: - use ADD not POP where possible - fix a couple of Thumb2 related issues - enable HAVE_FUNCTION_GRAPH_FP_TEST for robustness - enable the graph tracer with the EABI unwinder - avoid clobbering frame pointer registers to make Clang happy Link: https://lore.kernel.org/linux-arm-kernel/20220203082204.1176734-1-ardb@kernel.org/ 4) Fixes for the above. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuNNh8scc2k/wOAE+9OeQG+StrGQFAmI7U9IACgkQ9OeQG+St rGQghg/+PmgLJ9zmJrMGOarNLmmGzCbkPi6SrlbaDxriE7ofqo76qrQhGAsWxvDx OEYBNdWmOxTi7GP6sozFaTWrpD2ZbuFuKUUpusnjU2sMD/BwYHZZ/lKfZpn7WoE0 48e2FCFYsJ3sYpROhVgaFWk+64eVwHfZ7pr9pad1gAEB4SAaT+CiuXBsJCl4DBi7 eobYzLqETtCBkXFUo46n6r0xESdzQfgfZMsh5IpPRyswSPhzqdYrSLXJRmFGBqvT FS2gcMgd7IpcVsmd4pgFKe0Y9rBSuMEqsqYvzwSWI4GAgFppZO1R5RvHdS89US4P 9F6hgxYnJdc8hVhoAZNNi5cCcJp9th3Io97YzTUIm0xgK3nXyhsSGWIk3ahx76mX mnCcflUoOP9YVHUuoi1/N7iSe6xwtH+dg0Mn69aM4rNcZh5J59jV2rrNhdnr1Pjb XE8iQHJZATHZrxyAtj7PzlnNzJsfVcJyT/WieT0My7tZaZC0cICdKEJ6yurTlCvE v7P3EHUYFaQGkQijHFJdstkouY7SHpN0iH18xKErciWOwDmRsgVaoxw18iNIvuY/ TvSNXJBDgh8is8eV/mmN0iVkK0mYTxhy0G5CHavrgy8STWNC6CdqFtrxZnInoCAz wq25QvQtPZcxz1dS9bTuWUfrPATaIeQeCzUsAIiE7u9aP/olL5M= =AVCL -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm Pull ARM updates from Russell King: "Updates for IRQ stacks and virtually mapped stack support, and ftrace: - Support for IRQ and vmap'ed stacks This covers all the work related to implementing IRQ stacks and vmap'ed stacks for all 32-bit ARM systems that are currently supported by the Linux kernel, including RiscPC and Footbridge. It has been submitted for review in four different waves: - IRQ stacks support for v7 SMP systems [0] - vmap'ed stacks support for v7 SMP systems[1] - extending support for both IRQ stacks and vmap'ed stacks for all remaining configurations, including v6/v7 SMP multiplatform kernels and uniprocessor configurations including v7-M [2] - fixes and updates in [3] - ftrace fixes and cleanups Make all flavors of ftrace available on all builds, regardless of ISA choice, unwinder choice or compiler [4]: - use ADD not POP where possible - fix a couple of Thumb2 related issues - enable HAVE_FUNCTION_GRAPH_FP_TEST for robustness - enable the graph tracer with the EABI unwinder - avoid clobbering frame pointer registers to make Clang happy - Fixes for the above" [0] https://lore.kernel.org/linux-arm-kernel/20211115084732.3704393-1-ardb@kernel.org/ [1] https://lore.kernel.org/linux-arm-kernel/20211122092816.2865873-1-ardb@kernel.org/ [2] https://lore.kernel.org/linux-arm-kernel/20211206164659.1495084-1-ardb@kernel.org/ [3] https://lore.kernel.org/linux-arm-kernel/20220124174744.1054712-1-ardb@kernel.org/ [4] https://lore.kernel.org/linux-arm-kernel/20220203082204.1176734-1-ardb@kernel.org/ * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (62 commits) ARM: fix building NOMMU ARMv4/v5 kernels ARM: unwind: only permit stack switch when unwinding call_with_stack() ARM: Revert "unwind: dump exception stack from calling frame" ARM: entry: fix unwinder problems caused by IRQ stacks ARM: unwind: set frame.pc correctly for current-thread unwinding ARM: 9184/1: return_address: disable again for CONFIG_ARM_UNWIND=y ARM: 9183/1: unwind: avoid spurious warnings on bogus code addresses Revert "ARM: 9144/1: forbid ftrace with clang and thumb2_kernel" ARM: mach-bcm: disable ftrace in SMC invocation routines ARM: cacheflush: avoid clobbering the frame pointer ARM: kprobes: treat R7 as the frame pointer register in Thumb2 builds ARM: ftrace: enable the graph tracer with the EABI unwinder ARM: unwind: track location of LR value in stack frame ARM: ftrace: enable HAVE_FUNCTION_GRAPH_FP_TEST ARM: ftrace: avoid unnecessary literal loads ARM: ftrace: avoid redundant loads or clobbering IP ARM: ftrace: use trampolines to keep .init.text in branching range ARM: ftrace: use ADD not POP to counter PUSH at entry ARM: ftrace: ensure that ADR takes the Thumb bit into account ARM: make get_current() and __my_cpu_offset() __always_inline ...
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* drivers/irq/irq-nvic.c
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*
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* Copyright (C) 2008 ARM Limited, All Rights Reserved.
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* Copyright (C) 2013 Pengutronix
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*
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* Support for the Nested Vectored Interrupt Controller found on the
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* ARMv7-M CPUs (Cortex-M3/M4)
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <asm/v7m.h>
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#include <asm/exception.h>
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#define NVIC_ISER 0x000
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#define NVIC_ICER 0x080
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#define NVIC_IPR 0x400
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#define NVIC_MAX_BANKS 16
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/*
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* Each bank handles 32 irqs. Only the 16th (= last) bank handles only
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* 16 irqs.
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*/
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#define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
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static struct irq_domain *nvic_irq_domain;
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static void __irq_entry nvic_handle_irq(struct pt_regs *regs)
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{
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unsigned long icsr = readl_relaxed(BASEADDR_V7M_SCB + V7M_SCB_ICSR);
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irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16;
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generic_handle_domain_irq(nvic_irq_domain, hwirq);
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}
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static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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int i, ret;
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irq_hw_number_t hwirq;
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unsigned int type = IRQ_TYPE_NONE;
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struct irq_fwspec *fwspec = arg;
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ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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for (i = 0; i < nr_irqs; i++)
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irq_map_generic_chip(domain, virq + i, hwirq + i);
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return 0;
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}
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static const struct irq_domain_ops nvic_irq_domain_ops = {
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.translate = irq_domain_translate_onecell,
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.alloc = nvic_irq_domain_alloc,
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.free = irq_domain_free_irqs_top,
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};
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static int __init nvic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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unsigned int irqs, i, ret, numbanks;
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void __iomem *nvic_base;
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numbanks = (readl_relaxed(V7M_SCS_ICTR) &
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V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
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nvic_base = of_iomap(node, 0);
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if (!nvic_base) {
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pr_warn("unable to map nvic registers\n");
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return -ENOMEM;
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}
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irqs = numbanks * 32;
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if (irqs > NVIC_MAX_IRQ)
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irqs = NVIC_MAX_IRQ;
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nvic_irq_domain =
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irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
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if (!nvic_irq_domain) {
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pr_warn("Failed to allocate irq domain\n");
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iounmap(nvic_base);
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return -ENOMEM;
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}
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ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
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"nvic_irq", handle_fasteoi_irq,
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clr, 0, IRQ_GC_INIT_MASK_CACHE);
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if (ret) {
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pr_warn("Failed to allocate irq chips\n");
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irq_domain_remove(nvic_irq_domain);
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iounmap(nvic_base);
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return ret;
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}
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for (i = 0; i < numbanks; ++i) {
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struct irq_chip_generic *gc;
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gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
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gc->reg_base = nvic_base + 4 * i;
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gc->chip_types[0].regs.enable = NVIC_ISER;
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gc->chip_types[0].regs.disable = NVIC_ICER;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
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gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
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/* This is a no-op as end of interrupt is signaled by the
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* exception return sequence.
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*/
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gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
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/* disable interrupts */
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writel_relaxed(~0, gc->reg_base + NVIC_ICER);
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}
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/* Set priority on all interrupts */
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for (i = 0; i < irqs; i += 4)
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writel_relaxed(0, nvic_base + NVIC_IPR + i);
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set_handle_irq(nvic_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
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