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![Marc Zyngier](/assets/img/avatar_default.png)
Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
661 lines
17 KiB
C
661 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PRU-ICSS INTC IRQChip driver for various TI SoCs
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*
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* Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Author(s):
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* Andrew F. Davis <afd@ti.com>
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* Suman Anna <s-anna@ti.com>
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* Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments
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*
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* Copyright (C) 2019 David Lechner <david@lechnology.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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/*
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* Number of host interrupts reaching the main MPU sub-system. Note that this
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* is not the same as the total number of host interrupts supported by the PRUSS
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* INTC instance
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*/
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#define MAX_NUM_HOST_IRQS 8
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/* minimum starting host interrupt number for MPU */
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#define FIRST_PRU_HOST_INT 2
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/* PRU_ICSS_INTC registers */
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#define PRU_INTC_REVID 0x0000
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#define PRU_INTC_CR 0x0004
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#define PRU_INTC_GER 0x0010
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#define PRU_INTC_GNLR 0x001c
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#define PRU_INTC_SISR 0x0020
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#define PRU_INTC_SICR 0x0024
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#define PRU_INTC_EISR 0x0028
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#define PRU_INTC_EICR 0x002c
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#define PRU_INTC_HIEISR 0x0034
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#define PRU_INTC_HIDISR 0x0038
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#define PRU_INTC_GPIR 0x0080
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#define PRU_INTC_SRSR(x) (0x0200 + (x) * 4)
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#define PRU_INTC_SECR(x) (0x0280 + (x) * 4)
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#define PRU_INTC_ESR(x) (0x0300 + (x) * 4)
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#define PRU_INTC_ECR(x) (0x0380 + (x) * 4)
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#define PRU_INTC_CMR(x) (0x0400 + (x) * 4)
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#define PRU_INTC_HMR(x) (0x0800 + (x) * 4)
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#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4)
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#define PRU_INTC_SIPR(x) (0x0d00 + (x) * 4)
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#define PRU_INTC_SITR(x) (0x0d80 + (x) * 4)
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#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4)
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#define PRU_INTC_HIER 0x1500
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/* CMR register bit-field macros */
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#define CMR_EVT_MAP_MASK 0xf
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#define CMR_EVT_MAP_BITS 8
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#define CMR_EVT_PER_REG 4
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/* HMR register bit-field macros */
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#define HMR_CH_MAP_MASK 0xf
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#define HMR_CH_MAP_BITS 8
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#define HMR_CH_PER_REG 4
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/* HIPIR register bit-fields */
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#define INTC_HIPIR_NONE_HINT 0x80000000
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#define MAX_PRU_SYS_EVENTS 160
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#define MAX_PRU_CHANNELS 20
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/**
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* struct pruss_intc_map_record - keeps track of actual mapping state
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* @value: The currently mapped value (channel or host)
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* @ref_count: Keeps track of number of current users of this resource
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*/
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struct pruss_intc_map_record {
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u8 value;
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u8 ref_count;
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};
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/**
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* struct pruss_intc_match_data - match data to handle SoC variations
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* @num_system_events: number of input system events handled by the PRUSS INTC
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* @num_host_events: number of host events (which is equal to number of
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* channels) supported by the PRUSS INTC
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*/
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struct pruss_intc_match_data {
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u8 num_system_events;
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u8 num_host_events;
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};
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/**
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* struct pruss_intc - PRUSS interrupt controller structure
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* @event_channel: current state of system event to channel mappings
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* @channel_host: current state of channel to host mappings
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* @irqs: kernel irq numbers corresponding to PRUSS host interrupts
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* @base: base virtual address of INTC register space
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* @domain: irq domain for this interrupt controller
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* @soc_config: cached PRUSS INTC IP configuration data
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* @dev: PRUSS INTC device pointer
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* @lock: mutex to serialize interrupts mapping
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*/
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struct pruss_intc {
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struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS];
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struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS];
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unsigned int irqs[MAX_NUM_HOST_IRQS];
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void __iomem *base;
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struct irq_domain *domain;
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const struct pruss_intc_match_data *soc_config;
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struct device *dev;
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struct mutex lock; /* PRUSS INTC lock */
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};
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/**
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* struct pruss_host_irq_data - PRUSS host irq data structure
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* @intc: PRUSS interrupt controller pointer
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* @host_irq: host irq number
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*/
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struct pruss_host_irq_data {
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struct pruss_intc *intc;
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u8 host_irq;
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};
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static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
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{
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return readl_relaxed(intc->base + reg);
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}
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static inline void pruss_intc_write_reg(struct pruss_intc *intc,
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unsigned int reg, u32 val)
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{
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writel_relaxed(val, intc->base + reg);
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}
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static void pruss_intc_update_cmr(struct pruss_intc *intc, unsigned int evt,
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u8 ch)
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{
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u32 idx, offset, val;
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idx = evt / CMR_EVT_PER_REG;
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offset = (evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS;
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val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
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val &= ~(CMR_EVT_MAP_MASK << offset);
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val |= ch << offset;
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pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
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dev_dbg(intc->dev, "SYSEV%u -> CH%d (CMR%d 0x%08x)\n", evt, ch,
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idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
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}
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static void pruss_intc_update_hmr(struct pruss_intc *intc, u8 ch, u8 host)
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{
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u32 idx, offset, val;
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idx = ch / HMR_CH_PER_REG;
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offset = (ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS;
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val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
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val &= ~(HMR_CH_MAP_MASK << offset);
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val |= host << offset;
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pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
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dev_dbg(intc->dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx,
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pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
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}
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/**
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* pruss_intc_map() - configure the PRUSS INTC
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* @intc: PRUSS interrupt controller pointer
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* @hwirq: the system event number
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*
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* Configures the PRUSS INTC with the provided configuration from the one parsed
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* in the xlate function.
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*/
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static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq)
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{
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struct device *dev = intc->dev;
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u8 ch, host, reg_idx;
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u32 val;
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mutex_lock(&intc->lock);
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intc->event_channel[hwirq].ref_count++;
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ch = intc->event_channel[hwirq].value;
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host = intc->channel_host[ch].value;
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pruss_intc_update_cmr(intc, hwirq, ch);
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reg_idx = hwirq / 32;
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val = BIT(hwirq % 32);
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/* clear and enable system event */
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pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val);
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pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
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if (++intc->channel_host[ch].ref_count == 1) {
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pruss_intc_update_hmr(intc, ch, host);
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/* enable host interrupts */
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pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host);
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}
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dev_dbg(dev, "mapped system_event = %lu channel = %d host = %d",
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hwirq, ch, host);
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mutex_unlock(&intc->lock);
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}
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/**
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* pruss_intc_unmap() - unconfigure the PRUSS INTC
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* @intc: PRUSS interrupt controller pointer
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* @hwirq: the system event number
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*
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* Undo whatever was done in pruss_intc_map() for a PRU core.
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* Mappings are reference counted, so resources are only disabled when there
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* are no longer any users.
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*/
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static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq)
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{
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u8 ch, host, reg_idx;
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u32 val;
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mutex_lock(&intc->lock);
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ch = intc->event_channel[hwirq].value;
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host = intc->channel_host[ch].value;
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if (--intc->channel_host[ch].ref_count == 0) {
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/* disable host interrupts */
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pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host);
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/* clear the map using reset value 0 */
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pruss_intc_update_hmr(intc, ch, 0);
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}
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intc->event_channel[hwirq].ref_count--;
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reg_idx = hwirq / 32;
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val = BIT(hwirq % 32);
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/* disable system events */
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pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val);
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/* clear any pending status */
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pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
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/* clear the map using reset value 0 */
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pruss_intc_update_cmr(intc, hwirq, 0);
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dev_dbg(intc->dev, "unmapped system_event = %lu channel = %d host = %d\n",
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hwirq, ch, host);
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mutex_unlock(&intc->lock);
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}
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static void pruss_intc_init(struct pruss_intc *intc)
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{
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const struct pruss_intc_match_data *soc_config = intc->soc_config;
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int num_chnl_map_regs, num_host_intr_regs, num_event_type_regs, i;
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num_chnl_map_regs = DIV_ROUND_UP(soc_config->num_system_events,
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CMR_EVT_PER_REG);
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num_host_intr_regs = DIV_ROUND_UP(soc_config->num_host_events,
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HMR_CH_PER_REG);
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num_event_type_regs = DIV_ROUND_UP(soc_config->num_system_events, 32);
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/*
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* configure polarity (SIPR register) to active high and
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* type (SITR register) to level interrupt for all system events
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*/
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for (i = 0; i < num_event_type_regs; i++) {
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pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff);
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pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0);
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}
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/* clear all interrupt channel map registers, 4 events per register */
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for (i = 0; i < num_chnl_map_regs; i++)
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pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
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/* clear all host interrupt map registers, 4 channels per register */
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for (i = 0; i < num_host_intr_regs; i++)
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pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
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/* global interrupt enable */
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pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
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}
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static void pruss_intc_irq_ack(struct irq_data *data)
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{
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struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
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unsigned int hwirq = data->hwirq;
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pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
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}
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static void pruss_intc_irq_mask(struct irq_data *data)
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{
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struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
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unsigned int hwirq = data->hwirq;
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pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq);
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}
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static void pruss_intc_irq_unmask(struct irq_data *data)
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{
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struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
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unsigned int hwirq = data->hwirq;
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pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq);
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}
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static int pruss_intc_irq_reqres(struct irq_data *data)
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{
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if (!try_module_get(THIS_MODULE))
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return -ENODEV;
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return 0;
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}
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static void pruss_intc_irq_relres(struct irq_data *data)
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{
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module_put(THIS_MODULE);
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}
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static int pruss_intc_irq_get_irqchip_state(struct irq_data *data,
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enum irqchip_irq_state which,
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bool *state)
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{
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struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
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u32 reg, mask, srsr;
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if (which != IRQCHIP_STATE_PENDING)
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return -EINVAL;
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reg = PRU_INTC_SRSR(data->hwirq / 32);
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mask = BIT(data->hwirq % 32);
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srsr = pruss_intc_read_reg(intc, reg);
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*state = !!(srsr & mask);
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return 0;
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}
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static int pruss_intc_irq_set_irqchip_state(struct irq_data *data,
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enum irqchip_irq_state which,
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bool state)
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{
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struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
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if (which != IRQCHIP_STATE_PENDING)
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return -EINVAL;
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if (state)
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pruss_intc_write_reg(intc, PRU_INTC_SISR, data->hwirq);
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else
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pruss_intc_write_reg(intc, PRU_INTC_SICR, data->hwirq);
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return 0;
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}
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static struct irq_chip pruss_irqchip = {
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.name = "pruss-intc",
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.irq_ack = pruss_intc_irq_ack,
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.irq_mask = pruss_intc_irq_mask,
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.irq_unmask = pruss_intc_irq_unmask,
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.irq_request_resources = pruss_intc_irq_reqres,
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.irq_release_resources = pruss_intc_irq_relres,
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.irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state,
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.irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state,
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};
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static int pruss_intc_validate_mapping(struct pruss_intc *intc, int event,
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int channel, int host)
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{
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struct device *dev = intc->dev;
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int ret = 0;
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mutex_lock(&intc->lock);
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/* check if sysevent already assigned */
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if (intc->event_channel[event].ref_count > 0 &&
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intc->event_channel[event].value != channel) {
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dev_err(dev, "event %d (req. ch %d) already assigned to channel %d\n",
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event, channel, intc->event_channel[event].value);
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ret = -EBUSY;
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goto unlock;
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}
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/* check if channel already assigned */
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if (intc->channel_host[channel].ref_count > 0 &&
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intc->channel_host[channel].value != host) {
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dev_err(dev, "channel %d (req. host %d) already assigned to host %d\n",
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channel, host, intc->channel_host[channel].value);
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ret = -EBUSY;
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goto unlock;
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}
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intc->event_channel[event].value = channel;
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intc->channel_host[channel].value = host;
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unlock:
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mutex_unlock(&intc->lock);
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return ret;
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}
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static int
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pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
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{
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struct pruss_intc *intc = d->host_data;
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struct device *dev = intc->dev;
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int ret, sys_event, channel, host;
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if (intsize < 3)
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return -EINVAL;
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sys_event = intspec[0];
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if (sys_event < 0 || sys_event >= intc->soc_config->num_system_events) {
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dev_err(dev, "%d is not valid event number\n", sys_event);
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return -EINVAL;
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}
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channel = intspec[1];
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if (channel < 0 || channel >= intc->soc_config->num_host_events) {
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dev_err(dev, "%d is not valid channel number", channel);
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return -EINVAL;
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}
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host = intspec[2];
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if (host < 0 || host >= intc->soc_config->num_host_events) {
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dev_err(dev, "%d is not valid host irq number\n", host);
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return -EINVAL;
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}
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/* check if requested sys_event was already mapped, if so validate it */
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ret = pruss_intc_validate_mapping(intc, sys_event, channel, host);
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if (ret)
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return ret;
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*out_hwirq = sys_event;
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*out_type = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct pruss_intc *intc = d->host_data;
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|
|
pruss_intc_map(intc, hw);
|
|
|
|
irq_set_chip_data(virq, intc);
|
|
irq_set_chip_and_handler(virq, &pruss_irqchip, handle_level_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
|
|
{
|
|
struct pruss_intc *intc = d->host_data;
|
|
unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
|
|
|
|
irq_set_chip_and_handler(virq, NULL, NULL);
|
|
irq_set_chip_data(virq, NULL);
|
|
pruss_intc_unmap(intc, hwirq);
|
|
}
|
|
|
|
static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
|
|
.xlate = pruss_intc_irq_domain_xlate,
|
|
.map = pruss_intc_irq_domain_map,
|
|
.unmap = pruss_intc_irq_domain_unmap,
|
|
};
|
|
|
|
static void pruss_intc_irq_handler(struct irq_desc *desc)
|
|
{
|
|
unsigned int irq = irq_desc_get_irq(desc);
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct pruss_host_irq_data *host_irq_data = irq_get_handler_data(irq);
|
|
struct pruss_intc *intc = host_irq_data->intc;
|
|
u8 host_irq = host_irq_data->host_irq + FIRST_PRU_HOST_INT;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
while (true) {
|
|
u32 hipir;
|
|
int hwirq, err;
|
|
|
|
/* get highest priority pending PRUSS system event */
|
|
hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(host_irq));
|
|
if (hipir & INTC_HIPIR_NONE_HINT)
|
|
break;
|
|
|
|
hwirq = hipir & GENMASK(9, 0);
|
|
err = generic_handle_domain_irq(intc->domain, hwirq);
|
|
|
|
/*
|
|
* NOTE: manually ACK any system events that do not have a
|
|
* handler mapped yet
|
|
*/
|
|
if (WARN_ON_ONCE(err))
|
|
pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static const char * const irq_names[MAX_NUM_HOST_IRQS] = {
|
|
"host_intr0", "host_intr1", "host_intr2", "host_intr3",
|
|
"host_intr4", "host_intr5", "host_intr6", "host_intr7",
|
|
};
|
|
|
|
static int pruss_intc_probe(struct platform_device *pdev)
|
|
{
|
|
const struct pruss_intc_match_data *data;
|
|
struct device *dev = &pdev->dev;
|
|
struct pruss_intc *intc;
|
|
struct pruss_host_irq_data *host_data;
|
|
int i, irq, ret;
|
|
u8 max_system_events, irqs_reserved = 0;
|
|
|
|
data = of_device_get_match_data(dev);
|
|
if (!data)
|
|
return -ENODEV;
|
|
|
|
max_system_events = data->num_system_events;
|
|
|
|
intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
|
|
if (!intc)
|
|
return -ENOMEM;
|
|
|
|
intc->soc_config = data;
|
|
intc->dev = dev;
|
|
platform_set_drvdata(pdev, intc);
|
|
|
|
intc->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(intc->base))
|
|
return PTR_ERR(intc->base);
|
|
|
|
ret = of_property_read_u8(dev->of_node, "ti,irqs-reserved",
|
|
&irqs_reserved);
|
|
|
|
/*
|
|
* The irqs-reserved is used only for some SoC's therefore not having
|
|
* this property is still valid
|
|
*/
|
|
if (ret < 0 && ret != -EINVAL)
|
|
return ret;
|
|
|
|
pruss_intc_init(intc);
|
|
|
|
mutex_init(&intc->lock);
|
|
|
|
intc->domain = irq_domain_add_linear(dev->of_node, max_system_events,
|
|
&pruss_intc_irq_domain_ops, intc);
|
|
if (!intc->domain)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
|
|
if (irqs_reserved & BIT(i))
|
|
continue;
|
|
|
|
irq = platform_get_irq_byname(pdev, irq_names[i]);
|
|
if (irq <= 0) {
|
|
ret = (irq == 0) ? -EINVAL : irq;
|
|
goto fail_irq;
|
|
}
|
|
|
|
intc->irqs[i] = irq;
|
|
|
|
host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
|
|
if (!host_data) {
|
|
ret = -ENOMEM;
|
|
goto fail_irq;
|
|
}
|
|
|
|
host_data->intc = intc;
|
|
host_data->host_irq = i;
|
|
|
|
irq_set_handler_data(irq, host_data);
|
|
irq_set_chained_handler(irq, pruss_intc_irq_handler);
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail_irq:
|
|
while (--i >= 0) {
|
|
if (intc->irqs[i])
|
|
irq_set_chained_handler_and_data(intc->irqs[i], NULL,
|
|
NULL);
|
|
}
|
|
|
|
irq_domain_remove(intc->domain);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int pruss_intc_remove(struct platform_device *pdev)
|
|
{
|
|
struct pruss_intc *intc = platform_get_drvdata(pdev);
|
|
u8 max_system_events = intc->soc_config->num_system_events;
|
|
unsigned int hwirq;
|
|
int i;
|
|
|
|
for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
|
|
if (intc->irqs[i])
|
|
irq_set_chained_handler_and_data(intc->irqs[i], NULL,
|
|
NULL);
|
|
}
|
|
|
|
for (hwirq = 0; hwirq < max_system_events; hwirq++)
|
|
irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
|
|
|
|
irq_domain_remove(intc->domain);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pruss_intc_match_data pruss_intc_data = {
|
|
.num_system_events = 64,
|
|
.num_host_events = 10,
|
|
};
|
|
|
|
static const struct pruss_intc_match_data icssg_intc_data = {
|
|
.num_system_events = 160,
|
|
.num_host_events = 20,
|
|
};
|
|
|
|
static const struct of_device_id pruss_intc_of_match[] = {
|
|
{
|
|
.compatible = "ti,pruss-intc",
|
|
.data = &pruss_intc_data,
|
|
},
|
|
{
|
|
.compatible = "ti,icssg-intc",
|
|
.data = &icssg_intc_data,
|
|
},
|
|
{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
|
|
|
|
static struct platform_driver pruss_intc_driver = {
|
|
.driver = {
|
|
.name = "pruss-intc",
|
|
.of_match_table = pruss_intc_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = pruss_intc_probe,
|
|
.remove = pruss_intc_remove,
|
|
};
|
|
module_platform_driver(pruss_intc_driver);
|
|
|
|
MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
|
|
MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
|
|
MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>");
|
|
MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver");
|
|
MODULE_LICENSE("GPL v2");
|