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8de14b3acb
Commit 63839882c5 ("media: mach-pxa: palmz72/pcm990: remove soc_camera dependencies")
removed the last in-tree user of this sensor. New users
will be required to use the generic clock framework,
so it's possible to convert the driver to use it.
Convert the driver to use the CCF, and drop the legacy
v4l2-clk API.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Acked-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
207 lines
4.7 KiB
C
207 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* OmniVision OV96xx Camera Header File
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*
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* Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
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*/
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#ifndef __DRIVERS_MEDIA_VIDEO_OV9640_H__
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#define __DRIVERS_MEDIA_VIDEO_OV9640_H__
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/* Register definitions */
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#define OV9640_GAIN 0x00
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#define OV9640_BLUE 0x01
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#define OV9640_RED 0x02
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#define OV9640_VFER 0x03
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#define OV9640_COM1 0x04
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#define OV9640_BAVE 0x05
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#define OV9640_GEAVE 0x06
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#define OV9640_RSID 0x07
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#define OV9640_RAVE 0x08
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#define OV9640_COM2 0x09
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#define OV9640_PID 0x0a
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#define OV9640_VER 0x0b
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#define OV9640_COM3 0x0c
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#define OV9640_COM4 0x0d
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#define OV9640_COM5 0x0e
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#define OV9640_COM6 0x0f
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#define OV9640_AECH 0x10
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#define OV9640_CLKRC 0x11
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#define OV9640_COM7 0x12
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#define OV9640_COM8 0x13
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#define OV9640_COM9 0x14
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#define OV9640_COM10 0x15
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/* 0x16 - RESERVED */
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#define OV9640_HSTART 0x17
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#define OV9640_HSTOP 0x18
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#define OV9640_VSTART 0x19
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#define OV9640_VSTOP 0x1a
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#define OV9640_PSHFT 0x1b
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#define OV9640_MIDH 0x1c
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#define OV9640_MIDL 0x1d
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#define OV9640_MVFP 0x1e
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#define OV9640_LAEC 0x1f
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#define OV9640_BOS 0x20
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#define OV9640_GBOS 0x21
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#define OV9640_GROS 0x22
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#define OV9640_ROS 0x23
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#define OV9640_AEW 0x24
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#define OV9640_AEB 0x25
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#define OV9640_VPT 0x26
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#define OV9640_BBIAS 0x27
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#define OV9640_GBBIAS 0x28
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/* 0x29 - RESERVED */
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#define OV9640_EXHCH 0x2a
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#define OV9640_EXHCL 0x2b
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#define OV9640_RBIAS 0x2c
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#define OV9640_ADVFL 0x2d
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#define OV9640_ADVFH 0x2e
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#define OV9640_YAVE 0x2f
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#define OV9640_HSYST 0x30
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#define OV9640_HSYEN 0x31
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#define OV9640_HREF 0x32
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#define OV9640_CHLF 0x33
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#define OV9640_ARBLM 0x34
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/* 0x35..0x36 - RESERVED */
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#define OV9640_ADC 0x37
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#define OV9640_ACOM 0x38
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#define OV9640_OFON 0x39
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#define OV9640_TSLB 0x3a
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#define OV9640_COM11 0x3b
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#define OV9640_COM12 0x3c
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#define OV9640_COM13 0x3d
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#define OV9640_COM14 0x3e
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#define OV9640_EDGE 0x3f
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#define OV9640_COM15 0x40
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#define OV9640_COM16 0x41
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#define OV9640_COM17 0x42
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/* 0x43..0x4e - RESERVED */
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#define OV9640_MTX1 0x4f
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#define OV9640_MTX2 0x50
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#define OV9640_MTX3 0x51
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#define OV9640_MTX4 0x52
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#define OV9640_MTX5 0x53
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#define OV9640_MTX6 0x54
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#define OV9640_MTX7 0x55
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#define OV9640_MTX8 0x56
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#define OV9640_MTX9 0x57
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#define OV9640_MTXS 0x58
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/* 0x59..0x61 - RESERVED */
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#define OV9640_LCC1 0x62
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#define OV9640_LCC2 0x63
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#define OV9640_LCC3 0x64
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#define OV9640_LCC4 0x65
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#define OV9640_LCC5 0x66
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#define OV9640_MANU 0x67
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#define OV9640_MANV 0x68
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#define OV9640_HV 0x69
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#define OV9640_MBD 0x6a
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#define OV9640_DBLV 0x6b
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#define OV9640_GSP 0x6c /* ... till 0x7b */
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#define OV9640_GST 0x7c /* ... till 0x8a */
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#define OV9640_CLKRC_DPLL_EN 0x80
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#define OV9640_CLKRC_DIRECT 0x40
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#define OV9640_CLKRC_DIV(x) ((x) & 0x3f)
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#define OV9640_PSHFT_VAL(x) ((x) & 0xff)
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#define OV9640_ACOM_2X_ANALOG 0x80
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#define OV9640_ACOM_RSVD 0x12
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#define OV9640_MVFP_V 0x10
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#define OV9640_MVFP_H 0x20
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#define OV9640_COM1_HREF_NOSKIP 0x00
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#define OV9640_COM1_HREF_2SKIP 0x04
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#define OV9640_COM1_HREF_3SKIP 0x08
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#define OV9640_COM1_QQFMT 0x20
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#define OV9640_COM2_SSM 0x10
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#define OV9640_COM3_VP 0x04
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#define OV9640_COM4_QQ_VP 0x80
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#define OV9640_COM4_RSVD 0x40
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#define OV9640_COM5_SYSCLK 0x80
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#define OV9640_COM5_LONGEXP 0x01
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#define OV9640_COM6_OPT_BLC 0x40
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#define OV9640_COM6_ADBLC_BIAS 0x08
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#define OV9640_COM6_FMT_RST 0x82
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#define OV9640_COM6_ADBLC_OPTEN 0x01
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#define OV9640_COM7_RAW_RGB 0x01
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#define OV9640_COM7_RGB 0x04
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#define OV9640_COM7_QCIF 0x08
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#define OV9640_COM7_QVGA 0x10
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#define OV9640_COM7_CIF 0x20
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#define OV9640_COM7_VGA 0x40
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#define OV9640_COM7_SCCB_RESET 0x80
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#define OV9640_TSLB_YVYU_YUYV 0x04
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#define OV9640_TSLB_YUYV_UYVY 0x08
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#define OV9640_COM12_YUV_AVG 0x04
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#define OV9640_COM12_RSVD 0x40
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#define OV9640_COM13_GAMMA_NONE 0x00
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#define OV9640_COM13_GAMMA_Y 0x40
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#define OV9640_COM13_GAMMA_RAW 0x80
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#define OV9640_COM13_RGB_AVG 0x20
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#define OV9640_COM13_MATRIX_EN 0x10
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#define OV9640_COM13_Y_DELAY_EN 0x08
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#define OV9640_COM13_YUV_DLY(x) ((x) & 0x07)
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#define OV9640_COM15_OR_00FF 0x00
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#define OV9640_COM15_OR_01FE 0x40
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#define OV9640_COM15_OR_10F0 0xc0
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#define OV9640_COM15_RGB_NORM 0x00
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#define OV9640_COM15_RGB_565 0x10
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#define OV9640_COM15_RGB_555 0x30
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#define OV9640_COM16_RB_AVG 0x01
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/* IDs */
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#define OV9640_V2 0x9648
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#define OV9640_V3 0x9649
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#define VERSION(pid, ver) (((pid) << 8) | ((ver) & 0xFF))
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/* supported resolutions */
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enum {
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W_QQCIF = 88,
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W_QQVGA = 160,
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W_QCIF = 176,
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W_QVGA = 320,
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W_CIF = 352,
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W_VGA = 640,
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W_SXGA = 1280
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};
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#define H_SXGA 960
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/* Misc. structures */
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struct ov9640_reg_alt {
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u8 com7;
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u8 com12;
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u8 com13;
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u8 com15;
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};
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struct ov9640_reg {
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u8 reg;
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u8 val;
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};
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struct ov9640_priv {
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struct v4l2_subdev subdev;
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struct v4l2_ctrl_handler hdl;
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struct clk *clk;
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struct gpio_desc *gpio_power;
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struct gpio_desc *gpio_reset;
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int model;
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int revision;
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};
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#endif /* __DRIVERS_MEDIA_VIDEO_OV9640_H__ */
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