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![Krzysztof Kozlowski](/assets/img/avatar_default.png)
Printing probe success is discouraged, because we can use tracing for this purpose. Remove useless print message after Sunplus OCOTP driver probe. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220321110326.44652-3-krzk@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
226 lines
5.7 KiB
C
226 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* The OCOTP driver for Sunplus SP7021
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*
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* Copyright (C) 2019 Sunplus Technology Inc., All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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/*
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* OTP memory
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* Each bank contains 4 words (32 bits).
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* Bank 0 starts at offset 0 from the base.
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*/
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#define OTP_WORDS_PER_BANK 4
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#define OTP_WORD_SIZE sizeof(u32)
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#define OTP_BIT_ADDR_OF_BANK (8 * OTP_WORD_SIZE * OTP_WORDS_PER_BANK)
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#define QAC628_OTP_NUM_BANKS 8
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#define QAC628_OTP_SIZE (QAC628_OTP_NUM_BANKS * OTP_WORDS_PER_BANK * OTP_WORD_SIZE)
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#define OTP_READ_TIMEOUT_US 200000
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/* HB_GPIO */
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#define ADDRESS_8_DATA 0x20
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/* OTP_RX */
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#define OTP_CONTROL_2 0x48
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#define OTP_RD_PERIOD GENMASK(15, 8)
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#define OTP_RD_PERIOD_MASK ~GENMASK(15, 8)
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#define CPU_CLOCK FIELD_PREP(OTP_RD_PERIOD, 30)
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#define SEL_BAK_KEY2 BIT(5)
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#define SEL_BAK_KEY2_MASK ~BIT(5)
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#define SW_TRIM_EN BIT(4)
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#define SW_TRIM_EN_MASK ~BIT(4)
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#define SEL_BAK_KEY BIT(3)
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#define SEL_BAK_KEY_MASK ~BIT(3)
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#define OTP_READ BIT(2)
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#define OTP_LOAD_SECURE_DATA BIT(1)
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#define OTP_LOAD_SECURE_DATA_MASK ~BIT(1)
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#define OTP_DO_CRC BIT(0)
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#define OTP_DO_CRC_MASK ~BIT(0)
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#define OTP_STATUS 0x4c
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#define OTP_READ_DONE BIT(4)
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#define OTP_READ_DONE_MASK ~BIT(4)
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#define OTP_LOAD_SECURE_DONE_MASK ~BIT(2)
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#define OTP_READ_ADDRESS 0x50
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enum base_type {
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HB_GPIO,
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OTPRX,
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BASEMAX,
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};
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struct sp_ocotp_priv {
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struct device *dev;
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void __iomem *base[BASEMAX];
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struct clk *clk;
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};
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struct sp_ocotp_data {
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int size;
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};
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static const struct sp_ocotp_data sp_otp_v0 = {
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.size = QAC628_OTP_SIZE,
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};
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static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value)
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{
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unsigned int addr_data;
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unsigned int byte_shift;
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unsigned int status;
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int ret;
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addr_data = addr % (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
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addr_data = addr_data / OTP_WORD_SIZE;
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byte_shift = addr % (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
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byte_shift = byte_shift % OTP_WORD_SIZE;
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addr = addr / (OTP_WORD_SIZE * OTP_WORDS_PER_BANK);
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addr = addr * OTP_BIT_ADDR_OF_BANK;
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writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK &
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OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS);
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writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS);
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writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ,
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otp->base[OTPRX] + OTP_CONTROL_2);
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writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK
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& SEL_BAK_KEY_MASK & OTP_LOAD_SECURE_DATA_MASK & OTP_DO_CRC_MASK,
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otp->base[OTPRX] + OTP_CONTROL_2);
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writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK,
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otp->base[OTPRX] + OTP_CONTROL_2);
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ret = readl_poll_timeout(otp->base[OTPRX] + OTP_STATUS, status,
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status & OTP_READ_DONE, 10, OTP_READ_TIMEOUT_US);
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if (ret < 0)
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return ret;
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*value = (readl(otp->base[HB_GPIO] + ADDRESS_8_DATA + addr_data * OTP_WORD_SIZE)
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>> (8 * byte_shift)) & 0xff;
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return ret;
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}
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static int sp_ocotp_read(void *priv, unsigned int offset, void *value, size_t bytes)
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{
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struct sp_ocotp_priv *otp = priv;
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unsigned int addr;
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char *buf = value;
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char val[4];
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int ret;
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ret = clk_enable(otp->clk);
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if (ret)
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return ret;
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*buf = 0;
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for (addr = offset; addr < (offset + bytes); addr++) {
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ret = sp_otp_read_real(otp, addr, val);
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if (ret < 0) {
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dev_err(otp->dev, "OTP read fail:%d at %d", ret, addr);
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goto disable_clk;
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}
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*buf++ = *val;
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}
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disable_clk:
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clk_disable(otp->clk);
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return ret;
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}
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static struct nvmem_config sp_ocotp_nvmem_config = {
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.name = "sp-ocotp",
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.read_only = true,
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.word_size = 1,
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.size = QAC628_OTP_SIZE,
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.stride = 1,
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.reg_read = sp_ocotp_read,
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.owner = THIS_MODULE,
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};
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static int sp_ocotp_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct nvmem_device *nvmem;
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struct sp_ocotp_priv *otp;
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struct resource *res;
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int ret;
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otp = devm_kzalloc(dev, sizeof(*otp), GFP_KERNEL);
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if (!otp)
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return -ENOMEM;
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otp->dev = dev;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hb_gpio");
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otp->base[HB_GPIO] = devm_ioremap_resource(dev, res);
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if (IS_ERR(otp->base[HB_GPIO]))
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return PTR_ERR(otp->base[HB_GPIO]);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otprx");
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otp->base[OTPRX] = devm_ioremap_resource(dev, res);
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if (IS_ERR(otp->base[OTPRX]))
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return PTR_ERR(otp->base[OTPRX]);
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otp->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(otp->clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(otp->clk),
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"devm_clk_get fail\n");
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ret = clk_prepare(otp->clk);
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if (ret < 0) {
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dev_err(dev, "failed to prepare clk: %d\n", ret);
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return ret;
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}
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sp_ocotp_nvmem_config.priv = otp;
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sp_ocotp_nvmem_config.dev = dev;
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nvmem = devm_nvmem_register(dev, &sp_ocotp_nvmem_config);
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if (IS_ERR(nvmem))
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return dev_err_probe(&pdev->dev, PTR_ERR(nvmem),
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"register nvmem device fail\n");
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platform_set_drvdata(pdev, nvmem);
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dev_dbg(dev, "banks:%d x wpb:%d x wsize:%d = %d",
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(int)QAC628_OTP_NUM_BANKS, (int)OTP_WORDS_PER_BANK,
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(int)OTP_WORD_SIZE, (int)QAC628_OTP_SIZE);
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return 0;
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}
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static const struct of_device_id sp_ocotp_dt_ids[] = {
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{ .compatible = "sunplus,sp7021-ocotp", .data = &sp_otp_v0 },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sp_ocotp_dt_ids);
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static struct platform_driver sp_otp_driver = {
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.probe = sp_ocotp_probe,
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.driver = {
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.name = "sunplus,sp7021-ocotp",
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.of_match_table = sp_ocotp_dt_ids,
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}
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};
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module_platform_driver(sp_otp_driver);
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MODULE_AUTHOR("Vincent Shih <vincent.sunplus@gmail.com>");
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MODULE_DESCRIPTION("Sunplus On-Chip OTP driver");
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MODULE_LICENSE("GPL");
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