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![Andy Shevchenko](/assets/img/avatar_default.png)
The default values for hooks in the driver.pm are NULLs. Hence drop unused pch_pm_ops. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220207210730.75252-6-andriy.shevchenko@linux.intel.com Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
555 lines
12 KiB
C
555 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PTP 1588 clock using the EG20T PCH
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*
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* Copyright (C) 2010 OMICRON electronics GmbH
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* Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
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*
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* This code was derived from the IXP46X driver.
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/ptp_pch.h>
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#include <linux/slab.h>
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#define STATION_ADDR_LEN 20
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#define PCI_DEVICE_ID_PCH_1588 0x8819
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#define IO_MEM_BAR 1
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#define DEFAULT_ADDEND 0xA0000000
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#define TICKS_NS_SHIFT 5
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#define N_EXT_TS 2
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enum pch_status {
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PCH_SUCCESS,
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PCH_INVALIDPARAM,
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PCH_NOTIMESTAMP,
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PCH_INTERRUPTMODEINUSE,
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PCH_FAILED,
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PCH_UNSUPPORTED,
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};
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/*
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* struct pch_ts_regs - IEEE 1588 registers
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*/
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struct pch_ts_regs {
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u32 control;
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u32 event;
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u32 addend;
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u32 accum;
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u32 test;
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u32 ts_compare;
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u32 rsystime_lo;
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u32 rsystime_hi;
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u32 systime_lo;
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u32 systime_hi;
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u32 trgt_lo;
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u32 trgt_hi;
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u32 asms_lo;
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u32 asms_hi;
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u32 amms_lo;
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u32 amms_hi;
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u32 ch_control;
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u32 ch_event;
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u32 tx_snap_lo;
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u32 tx_snap_hi;
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u32 rx_snap_lo;
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u32 rx_snap_hi;
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u32 src_uuid_lo;
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u32 src_uuid_hi;
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u32 can_status;
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u32 can_snap_lo;
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u32 can_snap_hi;
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u32 ts_sel;
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u32 ts_st[6];
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u32 reserve1[14];
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u32 stl_max_set_en;
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u32 stl_max_set;
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u32 reserve2[13];
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u32 srst;
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};
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#define PCH_TSC_RESET (1 << 0)
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#define PCH_TSC_TTM_MASK (1 << 1)
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#define PCH_TSC_ASMS_MASK (1 << 2)
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#define PCH_TSC_AMMS_MASK (1 << 3)
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#define PCH_TSC_PPSM_MASK (1 << 4)
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#define PCH_TSE_TTIPEND (1 << 1)
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#define PCH_TSE_SNS (1 << 2)
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#define PCH_TSE_SNM (1 << 3)
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#define PCH_TSE_PPS (1 << 4)
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#define PCH_CC_MM (1 << 0)
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#define PCH_CC_TA (1 << 1)
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#define PCH_CC_MODE_SHIFT 16
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#define PCH_CC_MODE_MASK 0x001F0000
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#define PCH_CC_VERSION (1 << 31)
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#define PCH_CE_TXS (1 << 0)
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#define PCH_CE_RXS (1 << 1)
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#define PCH_CE_OVR (1 << 0)
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#define PCH_CE_VAL (1 << 1)
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#define PCH_ECS_ETH (1 << 0)
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#define PCH_ECS_CAN (1 << 1)
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#define PCH_IEEE1588_ETH (1 << 0)
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#define PCH_IEEE1588_CAN (1 << 1)
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/*
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* struct pch_dev - Driver private data
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*/
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struct pch_dev {
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struct pch_ts_regs __iomem *regs;
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info caps;
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int exts0_enabled;
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int exts1_enabled;
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u32 irq;
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struct pci_dev *pdev;
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spinlock_t register_lock;
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};
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/*
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* struct pch_params - 1588 module parameter
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*/
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struct pch_params {
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u8 station[STATION_ADDR_LEN];
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};
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/* structure to hold the module parameters */
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static struct pch_params pch_param = {
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"00:00:00:00:00:00"
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};
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/*
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* Register access functions
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*/
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static inline void pch_eth_enable_set(struct pch_dev *chip)
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{
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u32 val;
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/* SET the eth_enable bit */
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val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
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iowrite32(val, (&chip->regs->ts_sel));
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}
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static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
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{
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u64 ns;
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ns = ioread64_lo_hi(®s->systime_lo);
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return ns << TICKS_NS_SHIFT;
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}
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static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
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{
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iowrite64_lo_hi(ns >> TICKS_NS_SHIFT, ®s->systime_lo);
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}
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static inline void pch_block_reset(struct pch_dev *chip)
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{
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u32 val;
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/* Reset Hardware Assist block */
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val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
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iowrite32(val, (&chip->regs->control));
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val = val & ~PCH_TSC_RESET;
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iowrite32(val, (&chip->regs->control));
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}
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void pch_ch_control_write(struct pci_dev *pdev, u32 val)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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iowrite32(val, (&chip->regs->ch_control));
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}
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EXPORT_SYMBOL(pch_ch_control_write);
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u32 pch_ch_event_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u32 val;
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val = ioread32(&chip->regs->ch_event);
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return val;
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}
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EXPORT_SYMBOL(pch_ch_event_read);
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void pch_ch_event_write(struct pci_dev *pdev, u32 val)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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iowrite32(val, (&chip->regs->ch_event));
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}
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EXPORT_SYMBOL(pch_ch_event_write);
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u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u32 val;
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val = ioread32(&chip->regs->src_uuid_lo);
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return val;
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}
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EXPORT_SYMBOL(pch_src_uuid_lo_read);
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u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u32 val;
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val = ioread32(&chip->regs->src_uuid_hi);
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return val;
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}
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EXPORT_SYMBOL(pch_src_uuid_hi_read);
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u64 pch_rx_snap_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u64 ns;
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ns = ioread64_lo_hi(&chip->regs->rx_snap_lo);
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return ns << TICKS_NS_SHIFT;
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}
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EXPORT_SYMBOL(pch_rx_snap_read);
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u64 pch_tx_snap_read(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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u64 ns;
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ns = ioread64_lo_hi(&chip->regs->tx_snap_lo);
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return ns << TICKS_NS_SHIFT;
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}
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EXPORT_SYMBOL(pch_tx_snap_read);
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/* This function enables all 64 bits in system time registers [high & low].
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This is a work-around for non continuous value in the SystemTime Register*/
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static void pch_set_system_time_count(struct pch_dev *chip)
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{
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iowrite32(0x01, &chip->regs->stl_max_set_en);
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iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
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iowrite32(0x00, &chip->regs->stl_max_set_en);
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}
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static void pch_reset(struct pch_dev *chip)
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{
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/* Reset Hardware Assist */
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pch_block_reset(chip);
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/* enable all 32 bits in system time registers */
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pch_set_system_time_count(chip);
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}
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/**
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* pch_set_station_address() - This API sets the station address used by
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* IEEE 1588 hardware when looking at PTP
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* traffic on the ethernet interface
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* @addr: dress which contain the column separated address to be used.
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* @pdev: PCI device.
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*/
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int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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bool valid;
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u64 mac;
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/* Verify the parameter */
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if ((chip->regs == NULL) || addr == (u8 *)NULL) {
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dev_err(&pdev->dev,
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"invalid params returning PCH_INVALIDPARAM\n");
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return PCH_INVALIDPARAM;
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}
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valid = mac_pton(addr, (u8 *)&mac);
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if (!valid) {
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dev_err(&pdev->dev, "invalid params returning PCH_INVALIDPARAM\n");
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return PCH_INVALIDPARAM;
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}
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dev_dbg(&pdev->dev, "invoking pch_station_set\n");
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iowrite64_lo_hi(mac, &chip->regs->ts_st);
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return 0;
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}
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EXPORT_SYMBOL(pch_set_station_address);
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/*
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* Interrupt service routine
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*/
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static irqreturn_t isr(int irq, void *priv)
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{
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struct pch_dev *pch_dev = priv;
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struct pch_ts_regs __iomem *regs = pch_dev->regs;
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struct ptp_clock_event event;
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u32 ack = 0, val;
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val = ioread32(®s->event);
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if (val & PCH_TSE_SNS) {
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ack |= PCH_TSE_SNS;
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if (pch_dev->exts0_enabled) {
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event.type = PTP_CLOCK_EXTTS;
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event.index = 0;
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event.timestamp = ioread64_hi_lo(®s->asms_hi);
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event.timestamp <<= TICKS_NS_SHIFT;
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ptp_clock_event(pch_dev->ptp_clock, &event);
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}
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}
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if (val & PCH_TSE_SNM) {
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ack |= PCH_TSE_SNM;
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if (pch_dev->exts1_enabled) {
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event.type = PTP_CLOCK_EXTTS;
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event.index = 1;
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event.timestamp = ioread64_hi_lo(®s->asms_hi);
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event.timestamp <<= TICKS_NS_SHIFT;
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ptp_clock_event(pch_dev->ptp_clock, &event);
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}
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}
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if (val & PCH_TSE_TTIPEND)
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ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */
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if (ack) {
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iowrite32(ack, ®s->event);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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/*
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* PTP clock operations
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*/
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static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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u64 adj;
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u32 diff, addend;
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int neg_adj = 0;
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struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
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struct pch_ts_regs __iomem *regs = pch_dev->regs;
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if (ppb < 0) {
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neg_adj = 1;
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ppb = -ppb;
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}
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addend = DEFAULT_ADDEND;
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adj = addend;
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adj *= ppb;
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diff = div_u64(adj, 1000000000ULL);
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addend = neg_adj ? addend - diff : addend + diff;
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iowrite32(addend, ®s->addend);
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return 0;
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}
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static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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s64 now;
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unsigned long flags;
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struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
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struct pch_ts_regs __iomem *regs = pch_dev->regs;
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spin_lock_irqsave(&pch_dev->register_lock, flags);
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now = pch_systime_read(regs);
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now += delta;
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pch_systime_write(regs, now);
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spin_unlock_irqrestore(&pch_dev->register_lock, flags);
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return 0;
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}
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static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
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{
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u64 ns;
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unsigned long flags;
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struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
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struct pch_ts_regs __iomem *regs = pch_dev->regs;
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spin_lock_irqsave(&pch_dev->register_lock, flags);
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ns = pch_systime_read(regs);
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spin_unlock_irqrestore(&pch_dev->register_lock, flags);
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*ts = ns_to_timespec64(ns);
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return 0;
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}
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static int ptp_pch_settime(struct ptp_clock_info *ptp,
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const struct timespec64 *ts)
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{
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u64 ns;
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unsigned long flags;
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struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
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struct pch_ts_regs __iomem *regs = pch_dev->regs;
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ns = timespec64_to_ns(ts);
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spin_lock_irqsave(&pch_dev->register_lock, flags);
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pch_systime_write(regs, ns);
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spin_unlock_irqrestore(&pch_dev->register_lock, flags);
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return 0;
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}
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static int ptp_pch_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
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switch (rq->type) {
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case PTP_CLK_REQ_EXTTS:
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switch (rq->extts.index) {
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case 0:
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pch_dev->exts0_enabled = on ? 1 : 0;
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break;
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case 1:
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pch_dev->exts1_enabled = on ? 1 : 0;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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default:
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break;
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}
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return -EOPNOTSUPP;
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}
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static const struct ptp_clock_info ptp_pch_caps = {
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.owner = THIS_MODULE,
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.name = "PCH timer",
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.max_adj = 50000000,
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.n_ext_ts = N_EXT_TS,
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.n_pins = 0,
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.pps = 0,
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.adjfreq = ptp_pch_adjfreq,
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.adjtime = ptp_pch_adjtime,
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.gettime64 = ptp_pch_gettime,
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.settime64 = ptp_pch_settime,
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.enable = ptp_pch_enable,
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};
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static void pch_remove(struct pci_dev *pdev)
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{
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struct pch_dev *chip = pci_get_drvdata(pdev);
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free_irq(pdev->irq, chip);
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ptp_clock_unregister(chip->ptp_clock);
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}
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static s32
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pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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s32 ret;
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unsigned long flags;
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struct pch_dev *chip;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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return -ENOMEM;
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/* enable the 1588 pci device */
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ret = pcim_enable_device(pdev);
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if (ret != 0) {
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dev_err(&pdev->dev, "could not enable the pci device\n");
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return ret;
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}
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ret = pcim_iomap_regions(pdev, BIT(IO_MEM_BAR), "1588_regs");
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if (ret) {
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dev_err(&pdev->dev, "could not locate IO memory address\n");
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return ret;
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}
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/* get the virtual address to the 1588 registers */
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chip->regs = pcim_iomap_table(pdev)[IO_MEM_BAR];
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chip->caps = ptp_pch_caps;
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chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
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if (IS_ERR(chip->ptp_clock))
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return PTR_ERR(chip->ptp_clock);
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spin_lock_init(&chip->register_lock);
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ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
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if (ret != 0) {
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dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
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goto err_req_irq;
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}
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/* indicate success */
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chip->irq = pdev->irq;
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chip->pdev = pdev;
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pci_set_drvdata(pdev, chip);
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spin_lock_irqsave(&chip->register_lock, flags);
|
|
/* reset the ieee1588 h/w */
|
|
pch_reset(chip);
|
|
|
|
iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
|
|
iowrite64_lo_hi(1, &chip->regs->trgt_lo);
|
|
iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
|
|
|
|
pch_eth_enable_set(chip);
|
|
|
|
if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
|
|
if (pch_set_station_address(pch_param.station, pdev) != 0) {
|
|
dev_err(&pdev->dev,
|
|
"Invalid station address parameter\n"
|
|
"Module loaded but station address not set correctly\n"
|
|
);
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&chip->register_lock, flags);
|
|
return 0;
|
|
|
|
err_req_irq:
|
|
ptp_clock_unregister(chip->ptp_clock);
|
|
|
|
dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_PCH_1588
|
|
},
|
|
{0}
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pch_ieee1588_pcidev_id);
|
|
|
|
static struct pci_driver pch_driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.id_table = pch_ieee1588_pcidev_id,
|
|
.probe = pch_probe,
|
|
.remove = pch_remove,
|
|
};
|
|
module_pci_driver(pch_driver);
|
|
|
|
module_param_string(station,
|
|
pch_param.station, sizeof(pch_param.station), 0444);
|
|
MODULE_PARM_DESC(station,
|
|
"IEEE 1588 station address to use - colon separated hex values");
|
|
|
|
MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
|
|
MODULE_DESCRIPTION("PTP clock using the EG20T timer");
|
|
MODULE_LICENSE("GPL");
|